Displaying 4 results from an estimated 4 matches for "register>".
2019 Nov 22
2
Tablegen PAT limitation?
...p; string AsmString = "STORE $rs1, [$rbase + ( $roffset << $rshift )]";
list<dag> Pattern = [(store (v1i16 ?:$rs1), (add (v1i32 (bitconvert (i32 ?:$rbase))), (shl (v1i32 (sext (v1i16 ?:$roffset))), (v1i32 (build_vector (uimm2 ?:$rshift))))))];
list<Register> Uses = [];
list<Register> Defs = [];
int CodeSize = 0;
int AddedComplexity = 0;
bit isReturn = 0;
bit isBranch = 0;
bit isEHScopeReturn = 0;
------------------ Original ------------------
From:&...
2019 Nov 25
2
Tablegen PAT limitation?
..., Nov 22, 2019 09:51 PM
To: "Celine"<595602881 at qq.com>;"llvm-dev"<llvm-dev at lists.llvm.org>;
Subject: RE: Re:RE: Re:RE: Re:RE: [llvm-dev] Tablegen PAT limitation?
Thanks.
Looking at the InOperandList, the rs1, rbase, etc. have register class prefixes, e.g. MGPR:$rs1. In the pattern they don’t have them. The error you saw (“rs1 must be an identifier”) was caused by tablegen being unable to match the rs1 in the pattern with any of the instruction operands.
Could you change the pattern to
&nbs...
2019 Nov 21
2
Tablegen PAT limitation?
...m: llvm-dev <llvm-dev-bounces at lists.llvm.org> On Behalf Of Celine via llvm-dev
Sent: Tuesday, November 19, 2019 6:52 AM
To: llvm-dev <llvm-dev at lists.llvm.org>
Subject: [EXT] [llvm-dev] Tablegen PAT limitation?
Hello,
def GPR : RegisterClass<"ABC", [v1i16, v1f16], 16, (add
IA, IB, IC, ID, IE, IF, IG, IH
)>;
def MGPR : RegisterClass<"ABC", [v1i16, v1f16], 16, (add
IA, IB, IC, ID, IE, IF, IG, IH
&nbs...
2019 Nov 20
4
Tablegen PAT limitation?
...m: llvm-dev <llvm-dev-bounces at lists.llvm.org> On Behalf Of Celine via llvm-dev
Sent: Tuesday, November 19, 2019 6:52 AM
To: llvm-dev <llvm-dev at lists.llvm.org>
Subject: [EXT] [llvm-dev] Tablegen PAT limitation?
Hello,
def GPR : RegisterClass<"ABC", [v1i16, v1f16], 16, (add
IA, IB, IC, ID, IE, IF, IG, IH
)>;
def MGPR : RegisterClass<"ABC", [v1i16, v1f16], 16, (add
IA, IB, IC, ID, IE, IF, IG, IH
&nbs...