search for: regdef

Displaying 9 results from an estimated 9 matches for "regdef".

2013 Oct 22
1
[LLVMdev] System call miscompilation using the fast register allocator
...INLINEASM <es:> [sideeffect] [attdialect], $0:[reguse], %RSI %vreg7<def> = MOV64ri32 -1; GR64:%vreg7 %RDI<def> = COPY %vreg7; GR64:%vreg7 INLINEASM <es:> [sideeffect] [attdialect], $0:[reguse], %RDI INLINEASM <es:> [sideeffect] [attdialect], $0:[regdef], %RDI<imp-def> %vreg8<def> = COPY %RDI; GR64:%vreg8 %vreg2<def> = MOV64ri64i32 54; GR64:%vreg2 INLINEASM <es:> [sideeffect] [attdialect], $0:[regdef], %RSI<imp-def> %vreg9<def> = COPY %RSI; GR64:%vreg9 INLINEASM <es:> [sideeffect]...
2018 Dec 04
2
Incorrect placement of an instruction after PostRAScheduler pass
...0000 = 50.00%) BB#21(0x40000000 / 0x80000000 = 50.00%) …… BB#21: derived from LLVM BB %if.end Live Ins: %LR %R2 %R3 %R4 %R5 %R7 %R12 Predecessors according to CFG: BB#6 BB#20 BB#9 BB#14 INLINEASM <es:ldaexd $0, ${0:H}, [$1];> [sideeffect] [mayload] [maystore] [attdialect], $0:[regdef-ec:GPRPair], %R8_R9<earlyclobber,def>, $1:[reguse:GPR], %R4, <!3> %R0<def> = ANDri %R7, 1, pred:14, pred:%noreg, opt:%CPSR<def> %R0<def> = MOVr %LR, pred:1, pred:%CPSR<kill>, opt:%noreg %R1<def> = EORrr %R0, %LR, pred:14, pred:%noreg...
2007 Jul 29
1
klibc kernelheaders build failure on mips/mipsel
switching to newer linux-libc-dev linux-2.6 provided kernel headers worked fine beside on mips mipsel: In file included from usr/klibc/arch/mips/crt0.S:11: usr/include/arch/mips/machine/asm.h:8:24: error: asm/regdef.h: No such file or directory usr/include/arch/mips/machine/asm.h:9:21: error: asm/asm.h: No such file or directory i'm not sure if you want to export both headers in the make kernelheaders target or if it is the fault of klibc to assume that those are available? -- maks
2007 Aug 10
1
[LLVMdev] inline assembly
...there is no difference between input and output operands for memory constraints. can somebody confirm this? i could not find documentation on these flags, following the AddInlineAsmOperands it seems to be something like: 'Code | (Size << 3)' with Code on of these values: 1 REGUSE 2 REGDEF 3 IMM 4 MEM/ADDR are there any other values? and would it be safe to change 4 to MEMUSE and add 5 (MEMDEF)? i do not know where these values are used (except for the ISelDAG and the AsmPrinter). florian
2006 Jun 26
2
[klibc 28/43] mips support for klibc
...clude/arch/mips/machine/asm.h b/usr/include/arch/mips/machine/asm.h new file mode 100644 index 0000000..f524bc6 --- /dev/null +++ b/usr/include/arch/mips/machine/asm.h @@ -0,0 +1,11 @@ +/* + * arch/mips/include/machine/asm.h + */ + +#ifndef _MACHINE_ASM_H +#define _MACHINE_ASM_H + +#include <asm/regdef.h> +#include <asm/asm.h> + +#endif /* _MACHINE_ASM_H */ diff --git a/usr/include/arch/mips/sgidefs.h b/usr/include/arch/mips/sgidefs.h new file mode 100644 index 0000000..fba8ae8 --- /dev/null +++ b/usr/include/arch/mips/sgidefs.h @@ -0,0 +1,20 @@ +/* + * arch/mips/include/sgidefs.h + *...
2013 Jan 08
2
[LLVMdev] Inline asm bug?
...d from LLVM BB %entry Live Ins: %RDI %vreg0<def> = COPY %RDI; GR64:%vreg0 MOV32mi %RIP, 1, %noreg, <ga:@G>, %noreg, 0; mem:ST4[@G](tbaa=!"int") %vreg2<def> = COPY %vreg0; GR64:%vreg2,%vreg0 INLINEASM <es:> [attdialect], $0:[regdef:GR32], %vreg1<def>, $1:[reguse:GR64], %vreg2, $2:[clobber], %EFLAGS<earlyclobber,imp-def>, <<badref>>; GR32:%vreg1 GR64:%vreg2 %EAX<def> = COPY %vreg1; GR32:%vreg1 RET # End machine code for function foo. -Krzysztof -- Qualcomm Innovation Cen...
2013 Dec 05
3
[LLVMdev] X86 - Help on fixing a poor code generation bug
...k::iterator I = MBB.end(), E = MBB.begin(); + + while (I != E) { + --I; + if (I->hasUnmodeledSideEffects()) { + // Invalidate the Map. + Candidates.clear(); + continue; + } + + if (isValidCandidate(*I)) { + // Add this entry to the Candidates map. + unsigned RegDef = I->getOperand(0).getReg(); + Candidates.insert(std::make_pair(RegDef, I)); + continue; + } + + // Simplify according to the pattern + // X<def,tied1> = #OPCODE#SSrr X<kill,tied0>, Y + // Y<def,tied1> = #INSERT#SSrr Y<kill,tied0>, X<kill&gt...
2020 Feb 22
2
COPYs between register classes
Hi, On SystemZ there are a set of "access registers" that can be copied in and out of 32-bit GPRs with special instructions. These instructions can only perform the copy using low 32-bit parts of the 64-bit GPRs. As reported and discussed at https://bugs.llvm.org/show_bug.cgi?id=44254, this is currently broken due to the fact that the default register class for 32-bit integers is
2006 Jun 28
35
[klibc 00/31] klibc as a historyless patchset (updated and reorganized)
I have updated the klibc patchset based on feedback received. In particular, the patchset has been reorganized so as not to break git-bisect. Additionally, this updates the patch base to 2.6.17-git12 (d38b69689c349f35502b92e20dafb30c62d49d63) and klibc 1.4.8; the main difference on the klibc side is removal of obsolete code. This is also available as a git tree at: