Displaying 20 results from an estimated 29 matches for "regclass_iterator".
2008 Oct 13
2
[LLVMdev] INSERT_SUBREG node.
...you mentioned in
> v4= insert_subreg implicit_def, v1, 0
the following function returns an incorrect subregclass:
static const TargetRegisterClass*
getSubRegisterRegClass(const TargetRegisterClass *TRC, unsigned SubIdx)
{
// Pick the register class of the subregister
TargetRegisterInfo::regclass_iterator I =
TRC->subregclasses_begin() + SubIdx-1;
assert(I < TRC->subregclasses_end() &&
"Invalid subregister index for register class");
return *I;
}
what does -1 do while initializing I in the above fn?
TIA,
Sanjiv
2008 Oct 14
0
[LLVMdev] INSERT_SUBREG node.
...implicit_def, v1, 0
>
> the following function returns an incorrect subregclass:
>
> static const TargetRegisterClass*
> getSubRegisterRegClass(const TargetRegisterClass *TRC, unsigned
> SubIdx)
> {
> // Pick the register class of the subregister
> TargetRegisterInfo::regclass_iterator I =
> TRC->subregclasses_begin() + SubIdx-1;
> assert(I < TRC->subregclasses_end() &&
> "Invalid subregister index for register class");
> return *I;
> }
>
> what does -1 do while initializing I in the above fn?
>
> TIA,
> Sanjiv...
2011 Sep 12
3
[LLVMdev] Possible bug in SimpleRegisterCoalescing
...essarily crash or generate incorrect code for any of the supported targets.
I believe that there may be a problem in SimpleRegisterCoalescing::runOnMachineFunction where the allocatable registers for each register class are initialised for the function, i.e. the lines:
for (TargetRegisterInfo::regclass_iterator I = tri_->regclass_begin(),
E = tri_->regclass_end(); I != E; ++I)
allocatableRCRegs_.insert(std::make_pair(*I,
tri_->getAllocatableSet(fn, *I)));
If the allocatable registers are dependent on the function, such as might occur when...
2008 Oct 15
2
[LLVMdev] INSERT_SUBREG node.
...gClassList = [GR8];
}
Refer to below functions in ScheduleDAGEmit.cpp:
-----------------------------------------------
static const TargetRegisterClass*
getSubRegisterRegClass(const TargetRegisterClass *TRC, unsigned SubIdx)
{
// Pick the register class of the subregister
TargetRegisterInfo::regclass_iterator I =
TRC->subregclasses_begin() + SubIdx-1;
assert(I < TRC->subregclasses_end() &&
"Invalid subregister index for register class");
return *I;
}
/// getSuperRegisterRegClass - Returns the register class of a superreg
A whose
/// "SubIdx"'th...
2011 Sep 13
0
[LLVMdev] Possible bug in SimpleRegisterCoalescing
...enerate incorrect code for any of the supported targets.
>
> I believe that there may be a problem in SimpleRegisterCoalescing::runOnMachineFunction where the allocatable registers for each register class are initialised for the function, i.e. the lines:
>
> for (TargetRegisterInfo::regclass_iterator I = tri_->regclass_begin(),
> E = tri_->regclass_end(); I != E; ++I)
> allocatableRCRegs_.insert(std::make_pair(*I,
> tri_->getAllocatableSet(fn, *I)));
>
> If the allocatable registers are dependent on the function, su...
2006 Jul 02
0
[LLVMdev] Inserting move instruction
...nsigned src, unsigned
dst) {
MachineBasicBlock::iterator iter = mbb.getFirstTerminator();
const MRegisterInfo * reg_info =
this->machine_function->getTarget().getRegisterInfo();
// TODO: verify if does not causes incorrect allocation:
for(MRegisterInfo::regclass_iterator rcii = reg_info->regclass_begin(),
rcie = reg_info->regclass_end(); rcii != rcie; ++rcii) {
if( (*rcii)->contains(dst) ) {
rc = * rcii;
}
}
reg_info->copyRegToReg(mbb, iter, dst, src, rc);
}
Fernando
> > You can't d...
2006 Jul 02
2
[LLVMdev] Inserting move instruction
> On Sun, 2 Jul 2006, Fernando Magno Quintao Pereira wrote:
>
> > MachineBasicBlock::iterator iter = mbb.getFirstTerminator();
> > const TargetRegisterClass *rc = mf.getSSARegMap()->getRegClass(dst);
> > const MRegisterInfo * reg_info = mf.getTarget().getRegisterInfo();
> > reg_info->copyRegToReg(mbb, iter, dst, src, rc);
> > }
> >
>
2008 Oct 15
0
[LLVMdev] INSERT_SUBREG node.
...returns an incorrect subregclass:
>>>
>>> static const TargetRegisterClass*
>>> getSubRegisterRegClass(const TargetRegisterClass *TRC, unsigned
>>> SubIdx)
>>> {
>>> // Pick the register class of the subregister
>>> TargetRegisterInfo::regclass_iterator I =
>>> TRC->subregclasses_begin() + SubIdx-1;
>>> assert(I < TRC->subregclasses_end() &&
>>> "Invalid subregister index for register class");
>>> return *I;
>>> }
>>>
>>> what does -1 do while initia...
2011 Sep 19
1
[LLVMdev] Possible bug in SimpleRegisterCoalescing
...ct code for any of the supported targets.
>>
>> I believe that there may be a problem in SimpleRegisterCoalescing::runOnMachineFunction where the allocatable registers for each register class are initialised for the function, i.e. the lines:
>>
>> for (TargetRegisterInfo::regclass_iterator I = tri_->regclass_begin(),
>> E = tri_->regclass_end(); I != E; ++I)
>> allocatableRCRegs_.insert(std::make_pair(*I,
>> tri_->getAllocatableSet(fn, *I)));
>>
>> If the allocatable registers are dependent on...
2008 Oct 02
0
[LLVMdev] INSERT_SUBREG node.
On Oct 2, 2008, at 11:02 AM, Sanjiv.Gupta at microchip.com wrote:
> What’s the value produced by an INSERT_SUBREG node? Is it a chain?
No, insert_subreg returns a value:
v1 = insert_subreg v2, v3, idx
v1 and v2 will have the same type, e.g. i16, and v3 must have a sub-
register type, e.g. i8.
> Can I use to set a superreg of i16 type with two i8 values, and use
> the supperreg as
2008 Oct 02
2
[LLVMdev] INSERT_SUBREG node.
What's the value produced by an INSERT_SUBREG node? Is it a chain?
Can I use to set a superreg of i16 type with two i8 values, and use the
supperreg as an operand somewhere else?
- Sanjiv
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2008 Oct 15
3
[LLVMdev] INSERT_SUBREG node.
...> >>>
> >>> static const TargetRegisterClass*
> >>> getSubRegisterRegClass(const TargetRegisterClass *TRC, unsigned
> >>> SubIdx)
> >>> {
> >>> // Pick the register class of the subregister
> >>> TargetRegisterInfo::regclass_iterator I =
> >>> TRC->subregclasses_begin() + SubIdx-1;
> >>> assert(I < TRC->subregclasses_end() &&
> >>> "Invalid subregister index for register class");
> >>> return *I;
> >>> }
> >>>
> >&g...
2016 May 25
2
[GSoC 2016] Interprocedural Register Allocation - Introduction and Feedback
...register for given
target like AX, BX on X86.
>
> const TargetMachine &TM = MF.getTarget();
> const MCRegisterInfo *MCRI = TM.getMCRegisterInfo();
> DEBUG(dbgs() << "Function Name : " << MF.getName() << "\n");
>
> for(TargetRegisterInfo::regclass_iterator i = (*TRI).regclass_begin(), e =
> (*TRI).regclass_end(); i != e; i++ ) {
> for(TargetRegisterClass::iterator pregi = (*i)->begin(), prege =
> (*i)->end(); pregi != prege; pregi++ ) {
> DEBUG( dbgs() << "Physical Register : " << MCRI->getName(*pregi) <&...
2016 May 25
0
[GSoC 2016] Interprocedural Register Allocation - Introduction and Feedback
...&TM = MF.getTarget();
> >
>
> > > const MCRegisterInfo *MCRI = TM.getMCRegisterInfo();
> >
>
> > > DEBUG(dbgs() << "Function Name : " << MF.getName() << "\n");
> >
>
> > > for(TargetRegisterInfo::regclass_iterator i =
> > > (*TRI).regclass_begin(), e = (*TRI).regclass_end(); i != e; i++ )
> > > {
> >
>
> > > for(TargetRegisterClass::iterator pregi = (*i)->begin(), prege =
> > > (*i)->end(); pregi != prege; pregi++ ) {
> >
>
> > > DEBUG(...
2006 Jul 03
2
[LLVMdev] Inserting move instruction
...t) {
> MachineBasicBlock::iterator iter = mbb.getFirstTerminator();
> const MRegisterInfo * reg_info =
> this->machine_function->getTarget().getRegisterInfo();
>
> // TODO: verify if does not causes incorrect allocation:
> for(MRegisterInfo::regclass_iterator rcii = reg_info->regclass_begin(),
> rcie = reg_info->regclass_end(); rcii != rcie; ++rcii) {
> if( (*rcii)->contains(dst) ) {
> rc = * rcii;
> }
> }
>
> reg_info->copyRegToReg(mbb, iter, dst, src, rc);
> }
>...
2016 May 25
2
[GSoC 2016] Interprocedural Register Allocation - Introduction and Feedback
...ike AX, BX on X86.
>
>>
>> const TargetMachine &TM = MF.getTarget();
>> const MCRegisterInfo *MCRI = TM.getMCRegisterInfo();
>> DEBUG(dbgs() << "Function Name : " << MF.getName() << "\n");
>>
>> for(TargetRegisterInfo::regclass_iterator i = (*TRI).regclass_begin(), e
>> = (*TRI).regclass_end(); i != e; i++ ) {
>> for(TargetRegisterClass::iterator pregi = (*i)->begin(), prege =
>> (*i)->end(); pregi != prege; pregi++ ) {
>> DEBUG( dbgs() << "Physical Register : " << MCRI->getNa...
2008 Oct 16
0
[LLVMdev] INSERT_SUBREG node.
...>>>>> static const TargetRegisterClass*
>>>>> getSubRegisterRegClass(const TargetRegisterClass *TRC, unsigned
>>>>> SubIdx)
>>>>> {
>>>>> // Pick the register class of the subregister
>>>>> TargetRegisterInfo::regclass_iterator I =
>>>>> TRC->subregclasses_begin() + SubIdx-1;
>>>>> assert(I < TRC->subregclasses_end() &&
>>>>> "Invalid subregister index for register class");
>>>>> return *I;
>>>>> }
>>>>...
2016 May 25
0
[GSoC 2016] Interprocedural Register Allocation - Introduction and Feedback
...>>>
>>> const TargetMachine &TM = MF.getTarget();
>>> const MCRegisterInfo *MCRI = TM.getMCRegisterInfo();
>>> DEBUG(dbgs() << "Function Name : " << MF.getName() << "\n");
>>>
>>> for(TargetRegisterInfo::regclass_iterator i = (*TRI).regclass_begin(), e
>>> = (*TRI).regclass_end(); i != e; i++ ) {
>>> for(TargetRegisterClass::iterator pregi = (*i)->begin(), prege =
>>> (*i)->end(); pregi != prege; pregi++ ) {
>>> DEBUG( dbgs() << "Physical Register : " <<...
2016 May 24
0
[GSoC 2016] Interprocedural Register Allocation - Introduction and Feedback
...);
Some reason you can't use a const pointer here?
> const TargetMachine &TM = MF.getTarget();
> const MCRegisterInfo *MCRI = TM.getMCRegisterInfo();
> DEBUG(dbgs() << "Function Name : " << MF.getName() << "\n");
> for(TargetRegisterInfo::regclass_iterator i =
> (*TRI).regclass_begin(), e = (*TRI).regclass_end(); i != e; i++ ) {
> for(TargetRegisterClass::iterator pregi = (*i)->begin(), prege =
> (*i)->end(); pregi != prege; pregi++ ) {
> DEBUG( dbgs() << "Physical Register : " << MCRI->getName(*pregi) <&...
2016 May 25
2
[GSoC 2016] Interprocedural Register Allocation - Introduction and Feedback
...ter for given target like AX, BX on X86.
>
> const TargetMachine &TM = MF.getTarget();
> const MCRegisterInfo *MCRI = TM.getMCRegisterInfo();
> DEBUG(dbgs() << "Function Name : " << MF.getName() << "\n");
>
> for(TargetRegisterInfo::regclass_iterator i = (*TRI).regclass_begin(), e = (*TRI).regclass_end(); i != e; i++ ) {
> for(TargetRegisterClass::iterator pregi = (*i)->begin(), prege = (*i)->end(); pregi != prege; pregi++ ) {
> DEBUG( dbgs() << "Physical Register : " << MCRI->getName(*pregi) << &...