Displaying 20 results from an estimated 21 matches for "regclass_begin".
2011 Sep 12
3
[LLVMdev] Possible bug in SimpleRegisterCoalescing
...rrect code for any of the supported targets.
I believe that there may be a problem in SimpleRegisterCoalescing::runOnMachineFunction where the allocatable registers for each register class are initialised for the function, i.e. the lines:
for (TargetRegisterInfo::regclass_iterator I = tri_->regclass_begin(),
E = tri_->regclass_end(); I != E; ++I)
allocatableRCRegs_.insert(std::make_pair(*I,
tri_->getAllocatableSet(fn, *I)));
If the allocatable registers are dependent on the function, such as might occur when a frame pointer isn't r...
2011 Sep 13
0
[LLVMdev] Possible bug in SimpleRegisterCoalescing
...of the supported targets.
>
> I believe that there may be a problem in SimpleRegisterCoalescing::runOnMachineFunction where the allocatable registers for each register class are initialised for the function, i.e. the lines:
>
> for (TargetRegisterInfo::regclass_iterator I = tri_->regclass_begin(),
> E = tri_->regclass_end(); I != E; ++I)
> allocatableRCRegs_.insert(std::make_pair(*I,
> tri_->getAllocatableSet(fn, *I)));
>
> If the allocatable registers are dependent on the function, such as might occur when a fra...
2006 Jul 02
0
[LLVMdev] Inserting move instruction
...neBasicBlock::iterator iter = mbb.getFirstTerminator();
const MRegisterInfo * reg_info =
this->machine_function->getTarget().getRegisterInfo();
// TODO: verify if does not causes incorrect allocation:
for(MRegisterInfo::regclass_iterator rcii = reg_info->regclass_begin(),
rcie = reg_info->regclass_end(); rcii != rcie; ++rcii) {
if( (*rcii)->contains(dst) ) {
rc = * rcii;
}
}
reg_info->copyRegToReg(mbb, iter, dst, src, rc);
}
Fernando
> > You can't do it with this information. In som...
2006 Jul 02
2
[LLVMdev] Inserting move instruction
> On Sun, 2 Jul 2006, Fernando Magno Quintao Pereira wrote:
>
> > MachineBasicBlock::iterator iter = mbb.getFirstTerminator();
> > const TargetRegisterClass *rc = mf.getSSARegMap()->getRegClass(dst);
> > const MRegisterInfo * reg_info = mf.getTarget().getRegisterInfo();
> > reg_info->copyRegToReg(mbb, iter, dst, src, rc);
> > }
> >
>
2011 Sep 19
1
[LLVMdev] Possible bug in SimpleRegisterCoalescing
...d targets.
>>
>> I believe that there may be a problem in SimpleRegisterCoalescing::runOnMachineFunction where the allocatable registers for each register class are initialised for the function, i.e. the lines:
>>
>> for (TargetRegisterInfo::regclass_iterator I = tri_->regclass_begin(),
>> E = tri_->regclass_end(); I != E; ++I)
>> allocatableRCRegs_.insert(std::make_pair(*I,
>> tri_->getAllocatableSet(fn, *I)));
>>
>> If the allocatable registers are dependent on the function, such as might...
2016 May 25
2
[GSoC 2016] Interprocedural Register Allocation - Introduction and Feedback
...ke AX, BX on X86.
>
> const TargetMachine &TM = MF.getTarget();
> const MCRegisterInfo *MCRI = TM.getMCRegisterInfo();
> DEBUG(dbgs() << "Function Name : " << MF.getName() << "\n");
>
> for(TargetRegisterInfo::regclass_iterator i = (*TRI).regclass_begin(), e =
> (*TRI).regclass_end(); i != e; i++ ) {
> for(TargetRegisterClass::iterator pregi = (*i)->begin(), prege =
> (*i)->end(); pregi != prege; pregi++ ) {
> DEBUG( dbgs() << "Physical Register : " << MCRI->getName(*pregi) << " is
> modifie...
2016 May 25
0
[GSoC 2016] Interprocedural Register Allocation - Introduction and Feedback
...> > > const MCRegisterInfo *MCRI = TM.getMCRegisterInfo();
> >
>
> > > DEBUG(dbgs() << "Function Name : " << MF.getName() << "\n");
> >
>
> > > for(TargetRegisterInfo::regclass_iterator i =
> > > (*TRI).regclass_begin(), e = (*TRI).regclass_end(); i != e; i++ )
> > > {
> >
>
> > > for(TargetRegisterClass::iterator pregi = (*i)->begin(), prege =
> > > (*i)->end(); pregi != prege; pregi++ ) {
> >
>
> > > DEBUG( dbgs() << "Physical Register...
2006 Jul 03
2
[LLVMdev] Inserting move instruction
...or iter = mbb.getFirstTerminator();
> const MRegisterInfo * reg_info =
> this->machine_function->getTarget().getRegisterInfo();
>
> // TODO: verify if does not causes incorrect allocation:
> for(MRegisterInfo::regclass_iterator rcii = reg_info->regclass_begin(),
> rcie = reg_info->regclass_end(); rcii != rcie; ++rcii) {
> if( (*rcii)->contains(dst) ) {
> rc = * rcii;
> }
> }
>
> reg_info->copyRegToReg(mbb, iter, dst, src, rc);
> }
>
> Fernando
>
>>> Y...
2016 May 25
2
[GSoC 2016] Interprocedural Register Allocation - Introduction and Feedback
...gt;
>> const TargetMachine &TM = MF.getTarget();
>> const MCRegisterInfo *MCRI = TM.getMCRegisterInfo();
>> DEBUG(dbgs() << "Function Name : " << MF.getName() << "\n");
>>
>> for(TargetRegisterInfo::regclass_iterator i = (*TRI).regclass_begin(), e
>> = (*TRI).regclass_end(); i != e; i++ ) {
>> for(TargetRegisterClass::iterator pregi = (*i)->begin(), prege =
>> (*i)->end(); pregi != prege; pregi++ ) {
>> DEBUG( dbgs() << "Physical Register : " << MCRI->getName(*pregi) << "...
2016 May 25
0
[GSoC 2016] Interprocedural Register Allocation - Introduction and Feedback
...st TargetMachine &TM = MF.getTarget();
>>> const MCRegisterInfo *MCRI = TM.getMCRegisterInfo();
>>> DEBUG(dbgs() << "Function Name : " << MF.getName() << "\n");
>>>
>>> for(TargetRegisterInfo::regclass_iterator i = (*TRI).regclass_begin(), e
>>> = (*TRI).regclass_end(); i != e; i++ ) {
>>> for(TargetRegisterClass::iterator pregi = (*i)->begin(), prege =
>>> (*i)->end(); pregi != prege; pregi++ ) {
>>> DEBUG( dbgs() << "Physical Register : " << MCRI->getName(*pregi)...
2016 May 24
0
[GSoC 2016] Interprocedural Register Allocation - Introduction and Feedback
...const pointer here?
> const TargetMachine &TM = MF.getTarget();
> const MCRegisterInfo *MCRI = TM.getMCRegisterInfo();
> DEBUG(dbgs() << "Function Name : " << MF.getName() << "\n");
> for(TargetRegisterInfo::regclass_iterator i =
> (*TRI).regclass_begin(), e = (*TRI).regclass_end(); i != e; i++ ) {
> for(TargetRegisterClass::iterator pregi = (*i)->begin(), prege =
> (*i)->end(); pregi != prege; pregi++ ) {
> DEBUG( dbgs() << "Physical Register : " << MCRI->getName(*pregi) << "
> is modified &qu...
2016 May 25
2
[GSoC 2016] Interprocedural Register Allocation - Introduction and Feedback
...BX on X86.
>
> const TargetMachine &TM = MF.getTarget();
> const MCRegisterInfo *MCRI = TM.getMCRegisterInfo();
> DEBUG(dbgs() << "Function Name : " << MF.getName() << "\n");
>
> for(TargetRegisterInfo::regclass_iterator i = (*TRI).regclass_begin(), e = (*TRI).regclass_end(); i != e; i++ ) {
> for(TargetRegisterClass::iterator pregi = (*i)->begin(), prege = (*i)->end(); pregi != prege; pregi++ ) {
> DEBUG( dbgs() << "Physical Register : " << MCRI->getName(*pregi) << " is modified "&l...
2016 May 24
2
[GSoC 2016] Interprocedural Register Allocation - Introduction and Feedback
...sterInfo
*)MF.getSubtarget().getRegisterInfo();
const TargetMachine &TM = MF.getTarget();
const MCRegisterInfo *MCRI = TM.getMCRegisterInfo();
DEBUG(dbgs() << "Function Name : " << MF.getName() << "\n");
for(TargetRegisterInfo::regclass_iterator i = (*TRI).regclass_begin(), e =
(*TRI).regclass_end(); i != e; i++ ) {
for(TargetRegisterClass::iterator pregi = (*i)->begin(), prege =
(*i)->end(); pregi != prege; pregi++ ) {
DEBUG( dbgs() << "Physical Register : " << MCRI->getName(*pregi) << " is
modified "<< MRI->...
2016 May 25
3
[GSoC 2016] Interprocedural Register Allocation - Introduction and Feedback
...gt;> const TargetMachine &TM = MF.getTarget();
>> const MCRegisterInfo *MCRI = TM.getMCRegisterInfo();
>> DEBUG(dbgs() << "Function Name : " << MF.getName() << "\n");
>>
>> for(TargetRegisterInfo::regclass_iterator i = (*TRI).regclass_begin(), e = (*TRI).regclass_end(); i != e; i++ ) {
>> for(TargetRegisterClass::iterator pregi = (*i)->begin(), prege = (*i)->end(); pregi != prege; pregi++ ) {
>> DEBUG( dbgs() << "Physical Register : " << MCRI->getName(*pregi) << " is modified...
2016 May 25
0
[GSoC 2016] Interprocedural Register Allocation - Introduction and Feedback
...&TM = MF.getTarget();
>>>> const MCRegisterInfo *MCRI = TM.getMCRegisterInfo();
>>>> DEBUG(dbgs() << "Function Name : " << MF.getName() << "\n");
>>>>
>>>> for(TargetRegisterInfo::regclass_iterator i = (*TRI).regclass_begin(),
>>>> e = (*TRI).regclass_end(); i != e; i++ ) {
>>>> for(TargetRegisterClass::iterator pregi = (*i)->begin(), prege =
>>>> (*i)->end(); pregi != prege; pregi++ ) {
>>>> DEBUG( dbgs() << "Physical Register : " << MCRI->...
2016 May 25
2
[GSoC 2016] Interprocedural Register Allocation - Introduction and Feedback
...CRegisterInfo *MCRI = TM.getMCRegisterInfo();
>>>>>>>> DEBUG(dbgs() << "Function Name : " << MF.getName() << "\n");
>>>>>>>>
>>>>>>>> for(TargetRegisterInfo::regclass_iterator i = (*TRI).regclass_begin(), e = (*TRI).regclass_end(); i != e; i++ ) {
>>>>>>>> for(TargetRegisterClass::iterator pregi = (*i)->begin(), prege = (*i)->end(); pregi != prege; pregi++ ) {
>>>>>>>> DEBUG( dbgs() << "Physical Register : " << MCRI-...
2016 May 25
0
[GSoC 2016] Interprocedural Register Allocation - Introduction and Feedback
...tTarget();
>>>>> const MCRegisterInfo *MCRI = TM.getMCRegisterInfo();
>>>>> DEBUG(dbgs() << "Function Name : " << MF.getName() << "\n");
>>>>>
>>>>> for(TargetRegisterInfo::regclass_iterator i = (*TRI).regclass_begin(),
>>>>> e = (*TRI).regclass_end(); i != e; i++ ) {
>>>>> for(TargetRegisterClass::iterator pregi = (*i)->begin(), prege =
>>>>> (*i)->end(); pregi != prege; pregi++ ) {
>>>>> DEBUG( dbgs() << "Physical Register : " &...
2016 May 25
0
[GSoC 2016] Interprocedural Register Allocation - Introduction and Feedback
...gt; > > > >
> > > > > >
> > > > >
> > > >
> > >
> >
>
> > > > > > > > > > > for(TargetRegisterInfo::regclass_iterator i =
> > > > > > > > > > > (*TRI).regclass_begin(), e =
> > > > > > > > > > > (*TRI).regclass_end();
> > > > > > > > > > > i
> > > > > > > > > > > !=
> > > > > > > > > > > e;
> > > > > > > > &...
2009 Jan 07
4
[LLVMdev] Possible bug in the ARM backend?
...ne on a per function basis, because
// some registers may get included/excluded on a per
// function basic (e.g. frame pointer on X86)
regClass2AllowedSet.clear();
regClass2AllowedSet.resize(mri->getNumRegClasses() + 1);
for (TargetRegisterInfo::regclass_iterator
RCI = mri->regclass_begin(), RCE = mri->regclass_end();
RCI != RCE; ++RCI) {
int regClassId = (*RCI)->getID();
regClass2AllowedSet[regClassId].resize(mri->getNumRegs() + 1);
for (TargetRegisterClass::iterator I = (*RCI)->allocation_order_begin(*mf),
E =...
2016 May 18
0
[GSoC 2016] Interprocedural Register Allocation - Introduction and Feedback
> On May 18, 2016, at 11:00 AM, vivek pandya <vivekvpandya at gmail.com> wrote:
>
>
>
> Vivek Pandya
>
>
> On Wed, May 18, 2016 at 11:25 PM, Quentin Colombet <qcolombet at apple.com <mailto:qcolombet at apple.com>> wrote:
>
>> On May 18, 2016, at 10:46 AM, vivek pandya <vivekvpandya at gmail.com <mailto:vivekvpandya at