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regards_____
2013 Oct 05
1
OPUS implementation with FPGA
...kHz sampling rate and max
> 32 kbps. ____
>
> __ __
>
> What about implementing an OPUS coder and decoder in an FPGA? Has
> this been done? Would either coder or decoder more suitable for FPGA
> implementation? ____
>
> __ __
>
> Best regards____
>
> Fredrik Bonde____
>
> __ __
>
>
> _______________________________________________
> opus mailing list
> opus at xiph.org <mailto:opus at xiph.org>
> http://lists.xiph.org/mailman/listinfo/opus
>
>
>
>
> _________...
2013 Oct 04
3
OPUS implementation with FPGA
Hi,
We would like to use the OPUS codec @ 16 kHz sampling rate and max 32 kbps.
What about implementing an OPUS coder and decoder in an FPGA? Has this been done? Would either coder or decoder more suitable for FPGA implementation?
Best regards
Fredrik Bonde
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2011 Oct 18
3
Possible hint for "Clocksource tsc unstable" problem
Hello,
I made an interesting observation related to the "Clocksource tsc
unstable (delta = -2999660320319 ns)" problem. In the log of ntpd I found:
Oct 5 03:46:35 greenville-dom0 ntpd[4020]: kernel time sync status
change 6001
Oct 5 04:03:41 greenville-dom0 ntpd[4020]: kernel time sync status
change 2001
Oct 5 05:29:03 greenville-dom0 ntpd[4020]: kernel time sync status
change