Displaying 6 results from an estimated 6 matches for "reg_reg".
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2015 Aug 25
2
[LLVMdev] TableGen Register Class not matching for MI in 3.6
Here is the instruction in question:
multiclass AD<string asmstr, SDPatternOperator OpNode, RegisterClass
srcAReg,
RegisterClass dstReg, ValueType srcAType,
ValueType dstType, Operand ImmOd, ImmLeaf imm_type>
{
def REG_REG : SetADInOut<asmstr, srcAReg, dstReg,
[(set dstReg:$dstD, (OpNode srcAReg:$srcA))]>;
def IMM_REG : SetADInOut<asmstr, ImmOd, dstReg,
[(set dstReg:$dstD, (OpNode
imm_type:$srcA))]>;
def IMM_MEM : SetADIn<asmstr, Im...
2015 Aug 25
2
[LLVMdev] TableGen Register Class not matching for MI in 3.6
...rote:
>
> Here is the instruction in question:
>
> multiclass AD<string asmstr, SDPatternOperator OpNode, RegisterClass
> srcAReg,
> RegisterClass dstReg, ValueType srcAType,
> ValueType dstType, Operand ImmOd, ImmLeaf imm_type>
> {
> def REG_REG : SetADInOut<asmstr, srcAReg, dstReg,
> [(set dstReg:$dstD, (OpNode
> srcAReg:$srcA))]>;
> def IMM_REG : SetADInOut<asmstr, ImmOd, dstReg,
> [(set dstReg:$dstD, (OpNode
> imm_type:$srcA))]>;
> def IM...
2015 Aug 25
2
[LLVMdev] TableGen Register Class not matching for MI in 3.6
...instruction in question:
>>
>> multiclass AD<string asmstr, SDPatternOperator OpNode, RegisterClass
>> srcAReg,
>> RegisterClass dstReg, ValueType srcAType,
>> ValueType dstType, Operand ImmOd, ImmLeaf imm_type>
>> {
>> def REG_REG : SetADInOut<asmstr, srcAReg, dstReg,
>> [(set dstReg:$dstD, (OpNode
>> srcAReg:$srcA))]>;
>> def IMM_REG : SetADInOut<asmstr, ImmOd, dstReg,
>> [(set dstReg:$dstD, (OpNode
>> imm_type:$srcA))]&...
2015 Aug 25
2
[LLVMdev] TableGen Register Class not matching for MI in 3.6
...;>>
>>> multiclass AD<string asmstr, SDPatternOperator OpNode, RegisterClass
>>> srcAReg,
>>> RegisterClass dstReg, ValueType srcAType,
>>> ValueType dstType, Operand ImmOd, ImmLeaf imm_type>
>>> {
>>> def REG_REG : SetADInOut<asmstr, srcAReg, dstReg,
>>> [(set dstReg:$dstD, (OpNode
>>> srcAReg:$srcA))]>;
>>> def IMM_REG : SetADInOut<asmstr, ImmOd, dstReg,
>>> [(set dstReg:$dstD, (OpNode
>>>...
2015 Aug 25
2
[LLVMdev] TableGen Register Class not matching for MI in 3.6
...t; multiclass AD<string asmstr, SDPatternOperator OpNode, RegisterClass
>>>> srcAReg,
>>>> RegisterClass dstReg, ValueType srcAType,
>>>> ValueType dstType, Operand ImmOd, ImmLeaf imm_type>
>>>> {
>>>> def REG_REG : SetADInOut<asmstr, srcAReg, dstReg,
>>>> [(set dstReg:$dstD, (OpNode
>>>> srcAReg:$srcA))]>;
>>>> def IMM_REG : SetADInOut<asmstr, ImmOd, dstReg,
>>>> [(set dstReg:$dstD, (Op...
2015 Aug 25
4
[LLVMdev] TableGen Register Class not matching for MI in 3.6
Hi Ryan,
> On Aug 24, 2015, at 6:49 PM, Ryan Taylor <ryta1203 at gmail.com> wrote:
>
> Quentin,
>
> I apologize for the spamming here but in getVR (where VReg is assigned an RC), it calls:
>
> const TargetRegisterClass *RC = TLI->getRegClassFor(Op.getSimpleValueType());
> VReg = MRI->createVirtualRegister(RC);
>
> My question is why is it using the