Displaying 2 results from an estimated 2 matches for "reg8class".
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2015 Oct 30
2
Questions about load/store incrementing address modes
I have a rudimentary implementation for load and store instructions, where
the memory address operand is automatically post-incremented when the load
or store instruction is issued. However, this is currently coded using
custom lowering, and explicit pattern matching in the 'ISelDAGtoDAG'
implementation. But it seems to me that I ought to be able to achieve this
exclusively using
2015 Nov 02
2
Questions about load/store incrementing address modes
...ormed from a 16-bit register plus a zero-extended 8-bit register. I used a ComplexPattern to match the address expression and MIOperandInfo to specify the classes of the registers, e.g.
def memR16R8 : Operand<i16> {
let MIOperandInfo = (ops Reg16Class, Reg8Class);
...
}
Again, this seems to work OK for me.
Steve
On 30 Oct 2015, at 10:43, Martin J. O'Riordan via llvm-dev <llvm-dev at lists.llvm.org> wrote:
I have a rudimentary implementation for load and store instructions, where the memory add...