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2007 Oct 06
2
[LLVMdev] Spill Interval Generation Question
...ll code interval generation. The bug shows up when there's a copy that has its source register spilled. When the coalescer comes back around to try to coalesce the copy, the merge code complains that there are no values copied from the RHS. For example: Examining copy 256%reg1330 = MOVSSrr %reg1439<kill> MOVSSrr %reg1330<d> %reg1439 %reg1439 was created when a virtual register was spilled: Spilling register 1039 for live interval %reg1039,0 = [102,2340:0) 0 at 102 adding intervals for spills for interval: %reg1039,0 = [102,2340:0) 0 at 102 +[256,257:0) added new interv...