Displaying 5 results from an estimated 5 matches for "refnodes".
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2017 Oct 31
2
Reaching definitions on Machine IR post register allocation
Hi Venu,
FWIW, I have a pass that does copy propagation after RA [1] (currently
only within a basic block) that should be enabled some time in the
not-too-distant future. It has been reviewed and accepted, but I'm
currently working on getting a slight change to the MachineOperand
representation [2] that should make the copy propagation change much
simpler. I believe this change to
2017 Nov 01
2
Reaching definitions on Machine IR post register allocation
Hi Geoff/Krzyssztof,
Wouldn't the isRenamable() change be required even for the RDF based copy propagation? Maybe Hexagon does not impose ABI/ISA restrictions which require specific registers to be used in specific contexts.
Also, if Geoff's copy propagation pass is invoked post-RA wouldn't it need to handle the x86 ISA feature which allows 8 bit/16 bit values to be moved into a
2017 Nov 13
2
Reaching definitions on Machine IR post register allocation
...: Thu, Nov 2, 2017 at 1:34 AM
> Subject: Re: [llvm-dev] Reaching definitions on Machine IR post register
> allocation
> To: llvm-dev at lists.llvm.org <mailto:llvm-dev at lists.llvm.org>
>
>
> RDF has its own tests to detect the ability to rename any given
> register. RefNodes that have "Fixed" flag are those where the register
> cannot be changed. Having the isRenamable flag in MachineOperand would
> help remove these tests.
>
> -Krzysztof
>
>
>
>
> On 10/31/2017 11:24 PM, Raghavan, Venugopal via llvm-dev wrote:
>
>...
2017 Sep 12
6
Reaching definitions on Machine IR post register allocation
Hi Venu,
> On Sep 11, 2017, at 11:00 PM, Raghavan, Venugopal via llvm-dev <llvm-dev at lists.llvm.org> wrote:
>
> Hi Krzysztof,
>
> Thanks for your reply.
>
> I agree that adding extra register units for x86 would be the right way to fix this. Do you know if there is a plan to fix this?
No concrete plan, no. We've been thinking about for quite some time now, but
2017 Nov 24
2
Reaching definitions on Machine IR post register allocation
...Re: [llvm-dev] Reaching definitions on Machine IR post register
>>> allocation
>>> To: llvm-dev at lists.llvm.org <mailto:llvm-dev at lists.llvm.org>
>>>
>>>
>>> RDF has its own tests to detect the ability to rename any given
>>> register. RefNodes that have "Fixed" flag are those where the register
>>> cannot be changed. Having the isRenamable flag in MachineOperand would help
>>> remove these tests.
>>>
>>> -Krzysztof
>>>
>>>
>>>
>>>
>>> On 10/31/2017...