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...ttle-endian mode, the emitted code is a bit easier to understand if the 'correct' loads and stores are used. AltiVec is an implementation of big-endian vectors that doesn’t require multiple load instructions or shuffling bitcasts. See section 4.2 of http://www.freescale.com/files/32bit/doc/ref_manual/ALTIVECPIM.pdf I can’t tell if MIPS and ARM are doing the same thing, or if they need different models. I don’t think either has ever been attempted in LLVM. I suspect that some tinkering is required at the IR level as well to make it work. But it seems like we’ll probably need to allow the vecto...

> > Other big-endian targets may have similar issues, but I know virtually > > nothing about them. > > ARM's is an interesting implementation of big-endian vectors. AFAIK, other > architectures go all in and use both big-endian lanes and elements. That > makes the problem go away, and you only need one load instruction. The recently published MIPS SIMD Architecture