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i have already seen usage of __builtin_nontemporal_store but i want to automate identification of non temporal loads/stores. i think i need to go for a pass. is it possiblee to detect non temporal loops without polly? On Sat, Jan 20, 2018 at 11:26 PM, Simon Pilgrim <llvm-dev at redking.me.uk> wrote: > On 20/01/2018 18:16, hameeza ahmed wrote: > > Actually i am working on vector accelerator which will perform those > instructions which are non temporal. > > for instance if i have this loop > > for(i=0;i<2048;i++) > a[i]=b[i]+c[i]; > > cur...

...generally, I suspect that we'd need to split the loop so that small trip counts don't use them at all, and for larger trip counts, we don't disturb data-reuse opportunities that would otherwise exist.  -Hal > > On Sat, Jan 20, 2018 at 11:26 PM, Simon Pilgrim > <llvm-dev at redking.me.uk <mailto:llvm-dev at redking.me.uk>> wrote: > > On 20/01/2018 18:16, hameeza ahmed wrote: >> Actually i am working on vector accelerator which will perform >> those instructions which are non temporal. >> >> for instance if i have this...

On Sun, Jan 4, 2015 at 3:20 PM, Simon Pilgrim <llvm-dev at redking.me.uk> wrote: > On 24 Nov 2014, at 17:53, Chandler Carruth <chandlerc at gmail.com> wrote: > > > I'll be skimming the PRs to see if there are any really critical > regressions, but so far it looks pretty good. > > > > If you are actively disabling the new...

> On Jan 4, 2015, at 4:25 PM, Simon Pilgrim <llvm-dev at redking.me.uk> wrote: > > > On 4 Jan 2015, at 23:30, Chandler Carruth <chandlerc at gmail.com <mailto:chandlerc at gmail.com>> wrote: > >> On Sun, Jan 4, 2015 at 3:20 PM, Simon Pilgrim <llvm-dev at redking.me.uk <mailto:llvm-dev at redking.me.uk>> wrote: &...

...!tbaa !1, !nontemporal !1 so that i can offload load, add, store to accelerator hardware. is it possible here? do i need a separate pass to detect whether the loop has non temporal data or polly will help here? what do you say? On Sat, Jan 20, 2018 at 11:02 PM, Simon Pilgrim <llvm-dev at redking.me.uk> wrote: > On 20/01/2018 17:44, hameeza ahmed via llvm-dev wrote: > >> Hello, >> >> My work deals with non-temporal loads and stores i found non-temporal >> meta data in llvm documentation but its not shown in IR. >> >> How to get non-temporal m...

...;i<2048;i++) {   __builtin_nontemporal_store( __builtin_nontemporal_load(b+i) + __builtin_nontemporal_load(c + i), a + i ); } There may be an attribute you can tag pointers with instead but I don't know off hand. > On Sat, Jan 20, 2018 at 11:02 PM, Simon Pilgrim > <llvm-dev at redking.me.uk <mailto:llvm-dev at redking.me.uk>> wrote: > > On 20/01/2018 17:44, hameeza ahmed via llvm-dev wrote: > > Hello, > > My work deals with non-temporal loads and stores i found > non-temporal meta data in llvm documentation but its not...

On Tue, Sep 23, 2014 at 2:35 PM, Simon Pilgrim <llvm-dev at redking.me.uk> wrote: > If you don’t want to spend time on this, I’d be happy to create a > candidate patch for review? I’ve been unclear if you were taking patches > for your shuffle work prior to it becoming the default. While I'm happy to work on it, I'm even more happy to have...

On Sat, Feb 9, 2019 at 6:25 PM Simon Pilgrim <llvm-dev at redking.me.uk> wrote: > The add/sub (+mul) overflow intrinsics are being updated to support > vectors to match the related add/sub saturation intrinsics. We haven't > updated the docs yet as legalization, vectorization and various minor bits > of plumbing still need to be finished be...

...eventually we end up selecting the > sequence of vmovss+vpermilps. > > I hope this helps. > Andrea > > On Tue, Sep 23, 2014 at 10:53 PM, Chandler Carruth <chandlerc at google.com> > wrote: > > > > On Tue, Sep 23, 2014 at 2:35 PM, Simon Pilgrim <llvm-dev at redking.me.uk> > > wrote: > >> > >> If you don’t want to spend time on this, I’d be happy to create a > >> candidate patch for review? I’ve been unclear if you were taking > patches for > >> your shuffle work prior to it becoming the default. > > &gt...

On Sat, Sep 20, 2014 at 7:12 AM, Simon Pilgrim <llvm-dev at redking.me.uk> wrote: > Hi Andrea / Chandler / Quentin, > > If AVX is available I would expect the vpermilps/vpermilpd instruction to > be used for all float/double single vector shuffles, especially as it can > deal with the folded load case as well - this would avoid the integer/fl...

...ds, which essentially give a predicate of the lanes loaded successfully. For uncounted loops with these special loads, the loop predicate tests can be done using a 'ptest' instruction, checking if the last element is active. Amara On 3 February 2017 at 10:15, Simon Pilgrim <llvm-dev at redking.me.uk> wrote: > >> On 2 Feb 2017, at 01:06, Amara Emerson <amara.emerson at gmail.com> wrote: >>> >>> What stops us from doing so with intrinsics is just the knowledge, so >>> we trade complexity in the back-end to match long patterns for >>>...

On Sun, Sep 21, 2014 at 1:15 PM, Simon Pilgrim <llvm-dev at redking.me.uk> wrote: > On 20 Sep 2014, at 19:44, Chandler Carruth <chandlerc at google.com> wrote: > > > If AVX is available I would expect the vpermilps/vpermilpd instruction > to be used for all float/double single vector shuffles, especially as it > can deal with the fold...

Hi Matt, I can see a near future where perf-analysis tooling uses branch history profiler captures to determine how often loops/branches are taken and feeds that into llvm-mca, especially for hot/branchy loop analysis reports etc. Are you confident that your approach will be easily extendable for this? Similarly, being able to generally embed the profile markers in object libraries for

...t: Tuesday, February 18, 2020 12:14 PM > To: Nuno Lopes <nuno.lopes at ist.utl.pt> > Cc: 'Juneyoung Lee' <juneyoung.lee at sf.snu.ac.kr>; 'llvm-dev' <llvm- > dev at lists.llvm.org>; 'Roman Lebedev' <lebedev.ri at gmail.com>; llvm- > dev at redking.me.uk; Eli Friedman <efriedma at quicinc.com>; 'Philip Reames' > <listmail at philipreames.com>; Finkel, Hal J. <hfinkel at anl.gov>; 'Chung-Kil Hur' > <gil.hur at sf.snu.ac.kr>; 'John Regehr' <regehr at cs.utah.edu> > Subject: [EXT]...

...combine > see the add, 1. > > > > > > > > +Sanjay as well > > > > > > > > From: Amaury Séchet <deadalnix at gmail.com> > > Sent: Monday, August 26, 2019 10:48 AM > > To: Topper, Craig <craig.topper at intel.com>; llvm-dev at redking.me.uk; > efriedma at quicinc.com; lebedev.ri at gmail.com; llvm-dev < > llvm-dev at lists.llvm.org> > > Subject: LLVM X86 backend combineIncDecVector's transform > > > > > > > > Hi all, > > > > As you knwo already, I'm trying to chang...

...sBeforeLegalizeOps()? That would at least let the first DAG combine and the post type legalization DAG combine see the add, 1. +Sanjay as well From: Amaury Séchet <deadalnix at gmail.com> Sent: Monday, August 26, 2019 10:48 AM To: Topper, Craig <craig.topper at intel.com>; llvm-dev at redking.me.uk; efriedma at quicinc.com; lebedev.ri at gmail.com; llvm-dev <llvm-dev at lists.llvm.org> Subject: LLVM X86 backend combineIncDecVector's transform Hi all, As you knwo already, I'm trying to change DAGCombiner so that it process the nodes in topological order. Doing so is not...

...linux/builds/37730/steps/cmake%20stage%201/logs/stdio for Simon's example ICE. Best, Jinsong Ji (纪金松), PhD. XL/LLVM on Power Compiler Development E-mail: jji at us.ibm.com From: "Finkel, Hal J. via llvm-dev" <llvm-dev at lists.llvm.org> To: Simon Pilgrim <llvm-dev at redking.me.uk>, "llvm-dev at lists.llvm.org" <llvm-dev at lists.llvm.org>, "powerllvm at ca.ibm.com" <powerllvm at ca.ibm.com> Date: 09/01/2019 11:04 AM Subject: [EXTERNAL] Re: [llvm-dev] PowerPC Compiler Crash Sent by: "llvm-dev" <...

...r.DeSmalen at arm.com>; Zaks, Ayal <ayal.zaks at intel.com>; Graham Hunter <Graham.Hunter at arm.com>; Michael Kuperstein <mkuper at google.com>; Caballero, Diego <diego.caballero at intel.com>; Sanjay Patel <spatel at rotateright.com>; Simon Pilgrim <llvm-dev at redking.me.uk>; Tian, Xinmin <xinmin.tian at intel.com>; Nema, Ashutosh <Ashutosh.Nema at amd.com> Subject: Re: [llvm-dev] RFC: [LV] any objections in moving isLegalMasked* check from Legal to CostModel? (Cleaning up LoopVectorizationLegality) On 01/05/2018 06:28 PM, Saito, Hideki wrote...

Hi all, As you knwo already, I'm trying to change DAGCombiner so that it process the nodes in topological order. Doing so is not difficult per se, but this creates various improvements and regression to the existing test suite. I'd like to work through as many of the regressions as possible ahead of time. One source of such regressions is combineIncDecVector in the X86 backend. It

...r.DeSmalen at arm.com>; Zaks, Ayal <ayal.zaks at intel.com>; Graham Hunter <Graham.Hunter at arm.com>; Michael Kuperstein <mkuper at google.com>; Caballero, Diego <diego.caballero at intel.com>; Sanjay Patel <spatel at rotateright.com>; Simon Pilgrim <llvm-dev at redking.me.uk>; Tian, Xinmin <xinmin.tian at intel.com>; Nema, Ashutosh <Ashutosh.Nema at amd.com> Subject: Re: [llvm-dev] RFC: [LV] any objections in moving isLegalMasked* check from Legal to CostModel? (Cleaning up LoopVectorizationLegality) > On 5 Jan 2018, at 21:01, Saito, Hideki...