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On Jun 12, 2012, at 7:20 AM, Jordy Potman <jordy.potman at recoresystems.com> wrote: > > So in the volatile case the latency of the chain dependency is 0, while > in the non volatile case it is 1. > > I am using ScheduleDAGInstrs in a scheduler for a VLIW target and in the > volatile case the load gets incorrectly scheduled in the same cycle as &g...

Hi all, I have a question regarding the latency of the true dependency of a store followed by an aliased load in ScheduleDAGInstrs. The latency seems to depend on the store and load being volatile or not as can be seen in the post-RA-sched debug output of the attached ARM example: $ llc -O3 -debug-only=post-RA-sched store_load_latency_test.ll ... SU(2): STRi12 %R2<kill>,

Hi all, Thanks for your feed-backs :-) @Andrew: In fact, I've reused most of the postRA list scheduler code and the resource priority queue. Every time it needs to move forward, either because of a res hazard (HazardRec) or an invalid combination of instructions in the current packet (DFA), it closes the current bundle and advances to the next cycle. The non-interlocked nature of our

Hi all, We are using compiler-rt for floating point emulation on our DSP core. I am currently investigating two issues found by running TestFloat [1] on our core. The first issue is in __truncdfsf2. __truncdfsf2(0x1p+128) produces 0x1p-128, while the expected result is inf. __truncdfsf2(-0x1p+128) produces -0x1p-128, while the expected result is -inf. I think the condition of the else if on line