Displaying 7 results from an estimated 7 matches for "recoloring".
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precoloring
2007 Jan 13
0
Running KoolMoves 6.0 beta
Hello,
I'm running the most recent version of KoolMoves (a flash authoring
program) with pretty good success but for one thing so far: svg import.
Import is accurate as far as shape (node placement) but inaccurate with
respect to color. Specifically, pure blacks, pure whites, and gradients
are imported as gray. I'm able to recolor the gray elements in
KoolMoves, but the extra step
2007 Aug 06
0
[LLVMdev] Spillers
...rtest intervals precisely over each def/use of the original
interval. That is why they also have their weights set to #INF.
Imagine that on a second iteration allocation algorithm figures out that
some spilled interval can't be assigned a physical register. Allocator can't
spill it so some recoloring must be done to free at least one physical
register to allocate. Precoloring #INF weighted intervals makes allocation
simpler by eliminating such situations.
As for giving the best result. If assumed that each interval is spilled into
the shortest spill intervals then precoloring won't do any...
2017 Oct 26
3
RFC: Adding bit to register MachineOperands to allow post-RA register renaming
Forgive me if these questions are naive or if I'm misunderstanding
something. I'm certainly very interested in seeing the
MachineCopyPropagation patch finally land and stick.
1. Wouldn't function live-ins and reserved registers have started life as
physical registers already? For example, wouldn't a live-in be a copy from
a physical register to a virtual one allowing the flag to
2020 Mar 31
2
[ARM] Register pressure with -mthumb forces register reload before each call
Hi,
Compiling attached test-case, which is reduced version of of
uECC_shared_secret from tinycrypt library [1], with
--target=arm-linux-gnueabi -march=armv6-m -Oz -S
results in reloading of register holding function's address before
every call to blx:
ldr r3, .LCPI0_0
blx r3
mov r0, r6
mov r1, r5
mov r2, r4
ldr r3,
2020 Apr 07
2
[ARM] Register pressure with -mthumb forces register reload before each call
If I'm understanding what's going on in this test correctly, what's happening is:
* ARMTargetLowering::LowerCall prefers indirect calls when a function is called at least 3 times in minsize
* In thumb 1 (without -fno-omit-frame-pointer) we have effectively only 3 callee-saved registers (r4-r6)
* The function has three arguments, so those three plus the register we need to hold the
2007 Aug 06
5
[LLVMdev] Spillers
Can someone explain the theory behind the spillers in VirtRegMap.cpp?
It seems as though the spillers do triple duty:
- Insert load/store operations and/or fold instructions as necessary to carry
out spills
- Rewrite the spilled virtual registers to use machine registers (mapping
given by the caller in the VRM).
- Rewrite machine code to change virtual registers to physical registers
2020 Apr 15
4
[ARM] Register pressure with -mthumb forces register reload before each call
Hi,
I have attached WIP patch for adding foldMemoryOperand to Thumb1InstrInfo.
For the following case:
void f(int x, int y, int z)
{
void bar(int, int, int);
bar(x, y, z);
bar(x, z, y);
bar(y, x, z);
bar(y, y, x);
}
it calls foldMemoryOperand twice, and thus converts two calls from blx to bl.
callMI->dump() shows the function name "bar" correctly, however in
generated