Displaying 7 results from an estimated 7 matches for "recolor".
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precolor
2007 Jan 13
0
Running KoolMoves 6.0 beta
...ersion of KoolMoves (a flash authoring
program) with pretty good success but for one thing so far: svg import.
Import is accurate as far as shape (node placement) but inaccurate with
respect to color. Specifically, pure blacks, pure whites, and gradients
are imported as gray. I'm able to recolor the gray elements in
KoolMoves, but the extra step is of course tedious.
This may be a KoolMoves issue, but I did note these sorts of errors when
running from the console and thought I'd check to see if anything can be
done about them (me still being relatively new to both linux and wine):...
2007 Aug 06
0
[LLVMdev] Spillers
Hi, David.
Spill intervals must be precolored because they can't be spilled once more.
They are the shortest intervals precisely over each def/use of the original
interval. That is why they also have their weights set to #INF.
Imagine that on a second iteration allocation algorithm figures out that
some spilled interval can't be ass...
2017 Oct 26
3
RFC: Adding bit to register MachineOperands to allow post-RA register renaming
Forgive me if these questions are naive or if I'm misunderstanding
something. I'm certainly very interested in seeing the
MachineCopyPropagation patch finally land and stick.
1. Wouldn't function live-ins and reserved registers have started life as
physical registers already? For example, wouldn't a live-in be a copy from
a physical register to a virtual one allowing the flag to
2020 Mar 31
2
[ARM] Register pressure with -mthumb forces register reload before each call
...ht:INF
selectOrSplit tGPR:%16 [236r,240r:0) 0 at 236r weight:INF w=INF
Checking interference for %16 [236r,240r:0) 0 at 236r weight:INF
$r0: IK_RegUnit
$r1: IK_RegUnit
$r2: IK_RegUnit
$r3: IK_Free
assigning %16 to $r3: R3 [236r,240r:0) 0 at 236r
Trying to reconcile hints for: %2($r4)
%2($r4) is recolorable.
Trying to reconcile hints for: %1($r5)
%1($r5) is recolorable.
Trying to reconcile hints for: %0($r6)
%0($r6) is recolorable.
********** REWRITE VIRTUAL REGISTERS **********
********** Function: uECC_shared_secret
********** REGISTER MAP **********
[%0 -> $r6] tGPR
[%1 -> $r5] tGPR
[%2 -...
2020 Apr 07
2
[ARM] Register pressure with -mthumb forces register reload before each call
If I'm understanding what's going on in this test correctly, what's happening is:
* ARMTargetLowering::LowerCall prefers indirect calls when a function is called at least 3 times in minsize
* In thumb 1 (without -fno-omit-frame-pointer) we have effectively only 3 callee-saved registers (r4-r6)
* The function has three arguments, so those three plus the register we need to hold the
2007 Aug 06
5
[LLVMdev] Spillers
Can someone explain the theory behind the spillers in VirtRegMap.cpp?
It seems as though the spillers do triple duty:
- Insert load/store operations and/or fold instructions as necessary to carry
out spills
- Rewrite the spilled virtual registers to use machine registers (mapping
given by the caller in the VRM).
- Rewrite machine code to change virtual registers to physical registers
2020 Apr 15
4
[ARM] Register pressure with -mthumb forces register reload before each call
...%18 [324r,328r:0) 0 at 324r weight:INF
selectOrSplit tGPR:%18 [324r,328r:0) 0 at 324r weight:INF w=INF
hints: $r6
assigning %18 to $r6: R6 [324r,328r:0) 0 at 324r
Dropping unused %16 EMPTY weight:2.104167e-03
Dropping unused %10 EMPTY weight:INF
Trying to reconcile hints for: %0($r4)
%0($r4) is recolorable.
Trying to reconcile hints for: %1($r5)
%1($r5) is recolorable.
Trying to reconcile hints for: %2($r6)
%2($r6) is recolorable.
********** REWRITE VIRTUAL REGISTERS **********
********** Function: f
********** REGISTER MAP **********
[%0 -> $r4] tGPR
[%1 -> $r5] tGPR
[%2 -> $r6] tGPR
[%...