Displaying 9 results from an estimated 9 matches for "recognizableinstr".
2012 Jul 10
2
[LLVMdev] question on table gen TIED_TO constraint
...rm : AVX28I<opc, MRMSrcMem, (outs VR128:$dst, VR128:$mask_wb),
>> (ins VR128:$src1, v128mem:$src2, VR128:$mask),
>> ...
>> }
>> There is a problem since MRMSrcMem assumes the 2nd physical operand is a memory operand.
>> See the section about MRMSrcMem in RecognizableInstr::emitInstructionSpecifier.
>
> Can this be fixed?
>
> Evan
>
>> And the above gives us $dst, $mask_wb, $src1, $mem, $mask, and $mask_wb is the second physical operand.
>>
>> I thought about using "$mask_wb = $mask", but it breaks the assumption of TIED...
2012 Jul 09
2
[LLVMdev] question on table gen TIED_TO constraint
...$dst, $mask = $mask_wb" in {
...
def rm : AVX28I<opc, MRMSrcMem, (outs VR128:$dst, VR128:$mask_wb),
(ins VR128:$src1, v128mem:$src2, VR128:$mask),
...
}
There is a problem since MRMSrcMem assumes the 2nd physical operand is a memory operand.
See the section about MRMSrcMem in RecognizableInstr::emitInstructionSpecifier.
And the above gives us $dst, $mask_wb, $src1, $mem, $mask, and $mask_wb is the second physical operand.
I thought about using "$mask_wb = $mask", but it breaks the assumption of TIED_TO LhsIdx > RhsIdx.
Is adding another addressing mode a good idea?
Any poi...
2012 Jul 10
0
[LLVMdev] question on table gen TIED_TO constraint
...uts VR128:$dst, VR128:$mask_wb),
> >> (ins VR128:$src1, v128mem:$src2, VR128:$mask),
> >> ...
> >> }
> >> There is a problem since MRMSrcMem assumes the 2nd physical operand is
> a memory operand.
> >> See the section about MRMSrcMem in
> RecognizableInstr::emitInstructionSpecifier.
> >
> > Can this be fixed?
> >
> > Evan
> >
> >> And the above gives us $dst, $mask_wb, $src1, $mem, $mask, and $mask_wb
> is the second physical operand.
> >>
> >> I thought about using "$mask_wb = $mask&qu...
2012 Jul 10
0
[LLVMdev] question on table gen TIED_TO constraint
...> ...
> def rm : AVX28I<opc, MRMSrcMem, (outs VR128:$dst, VR128:$mask_wb),
> (ins VR128:$src1, v128mem:$src2, VR128:$mask),
> ...
> }
> There is a problem since MRMSrcMem assumes the 2nd physical operand is a memory operand.
> See the section about MRMSrcMem in RecognizableInstr::emitInstructionSpecifier.
Can this be fixed?
Evan
> And the above gives us $dst, $mask_wb, $src1, $mem, $mask, and $mask_wb is the second physical operand.
>
> I thought about using "$mask_wb = $mask", but it breaks the assumption of TIED_TO LhsIdx > RhsIdx.
> Is addin...
2017 Sep 04
2
Issues in Vector Add Instruction Machine Code Emission
Thank You.
I used EVEX_4V with all the instructions. I replaced TA and EVEX both with
EVEX_4V. Now, I am getting following error:
llvm-tblgen: /utils/TableGen/X86RecognizableInstr.cpp:687: void
llvm::X86Disassembler::RecognizableInstr::emitInstructionSpecifier():
Assertion `numPhysicalOperands >= 2 + additionalOperands &&
numPhysicalOperands <= 4 + additionalOperands && "Unexpected number of
operands for MRMSrcMemFrm"' failed
What to do n...
2017 Sep 05
2
Issues in Vector Add Instruction Machine Code Emission
...4, 2017 at 4:28 PM, hameeza ahmed <hahmed2305 at gmail.com>
> wrote:
>
>> Thank You.
>>
>> I used EVEX_4V with all the instructions. I replaced TA and EVEX both
>> with EVEX_4V. Now, I am getting following error:
>>
>> llvm-tblgen: /utils/TableGen/X86RecognizableInstr.cpp:687: void
>> llvm::X86Disassembler::RecognizableInstr::emitInstructionSpecifier():
>> Assertion `numPhysicalOperands >= 2 + additionalOperands &&
>> numPhysicalOperands <= 4 + additionalOperands && "Unexpected number of
>> operands for MRMSrcMe...
2017 Sep 05
2
Issues in Vector Add Instruction Machine Code Emission
...t;
>>> wrote:
>>>
>>>> Thank You.
>>>>
>>>> I used EVEX_4V with all the instructions. I replaced TA and EVEX both
>>>> with EVEX_4V. Now, I am getting following error:
>>>>
>>>> llvm-tblgen: /utils/TableGen/X86RecognizableInstr.cpp:687: void
>>>> llvm::X86Disassembler::RecognizableInstr::emitInstructionSpecifier():
>>>> Assertion `numPhysicalOperands >= 2 + additionalOperands &&
>>>> numPhysicalOperands <= 4 + additionalOperands && "Unexpected number of
>&g...
2017 Aug 07
3
VBROADCAST Implementation Issues
...rc1), VK64WM:$mask,
addr:$src2)))],
IIC_MOV_MEM>, TA;
def: Pat<(v64f32 (masked_gather (VR_2048:$src1),
(VK64WM:$mask),(addr:$src2))), (GATHER_256B VR_2048:$src1, VK64WM:$mask,
addr:$src2)>;
Now getting this error:
llvm-tblgen: /utils/TableGen/X86RecognizableInstr.cpp:687: void
llvm::X86Disassembler::RecognizableInstr::emitInstructionSpecifier():
Assertion `numPhysicalOperands >= 2 + additionalOperands &&
numPhysicalOperands <= 4 + additionalOperands && "Unexpected number of
operands for MRMSrcMemFrm"' failed.
On M...
2017 Sep 04
2
Issues in Vector Add Instruction Machine Code Emission
Sorry to ask but what does it mean to put both?
On Tue, Sep 5, 2017 at 4:01 AM, Craig Topper <craig.topper at gmail.com> wrote:
> Leave TA. Put both.
>
> ~Craig
>
> On Mon, Sep 4, 2017 at 4:00 PM, hameeza ahmed <hahmed2305 at gmail.com>
> wrote:
>
>> You are right. But when i defined my instruction as follows:
>> def P_256B_VADD : I<0xE1,