search for: reclustering

...ster centers and save the cluster centers to a file [1]. This first data set is huge, it is guarantied that cluster centers will converge. Afterwards I load my cluster centers and cluster via k-means all other datasets with the same cluster centers [2]. I tried this but now I'm getting in the reclustering step following error message: "Error: empty cluster: try a better set of initial centers" That one of the clusters is empty (has no datapoint) should not be a problem. This can happen because the new data sets can be smaller. What am I doing wrong? Is there a other way to cluster new da...

...egister allocation. I used the following pass order for the clustered VLIW back-end: DAG->DAG Pattern Instruction Selection ... Clustering (Not required for unicluster VLIW architectures) Scheduling Packing ... Register Allocation ... Prolog/Epilog Insertion & Frame Finalization Unpacking Reclustering ... Rescheduling (Splitting, Packing, Scheduling, Unpacking) Assembly Printer In principle, it is possible to use the LLVM scheduler to generate parallel code by providing a custom hazard recognizer that checks true data dependencies of the current bundle. The scheduler has also the capability to...

...clustered VLIW back-end: > > DAG->DAG Pattern Instruction Selection > ... > Clustering (Not required for unicluster VLIW architectures) > Scheduling > Packing > ... > Register Allocation > ... > Prolog/Epilog Insertion & Frame Finalization > Unpacking > Reclustering > ... > Rescheduling (Splitting, Packing, Scheduling, Unpacking) > Assembly Printer > > > In principle, it is possible to use the LLVM scheduler to generate parallel code by providing a custom hazard recognizer that checks true data dependencies of the current bundle. The schedu...

Hi all, here is the current (unfinished) version of the VLIW support I mentioned. It is a patch over svn rev 141176. It includes the MachineInstrBundle class, and small required changes in a couple of outside LLVM files. Also includes a modification to Mips target to simulate a 2-wide VLIW MIPS. The scheduler is really silly, I did not want to implement a scheduler, just the bundle class, and

...clustered VLIW back-end: > > DAG->DAG Pattern Instruction Selection > ... > Clustering (Not required for unicluster VLIW architectures) > Scheduling > Packing > ... > Register Allocation > ... > Prolog/Epilog Insertion & Frame Finalization > Unpacking > Reclustering > ... > Rescheduling (Splitting, Packing, Scheduling, Unpacking) > Assembly Printer > > > In principle, it is possible to use the LLVM scheduler to generate parallel code by providing a custom hazard recognizer that checks true data dependencies of the current bundle. The schedu...

...->DAG Pattern Instruction Selection >> ... >> Clustering (Not required for unicluster VLIW architectures) >> Scheduling >> Packing >> ... >> Register Allocation >> ... >> Prolog/Epilog Insertion & Frame Finalization >> Unpacking >> Reclustering >> ... >> Rescheduling (Splitting, Packing, Scheduling, Unpacking) >> Assembly Printer >> >> >> In principle, it is possible to use the LLVM scheduler to generate parallel code by providing a custom hazard recognizer that checks true data dependencies of the cu...

...->DAG Pattern Instruction Selection >> ... >> Clustering (Not required for unicluster VLIW architectures) >> Scheduling >> Packing >> ... >> Register Allocation >> ... >> Prolog/Epilog Insertion & Frame Finalization >> Unpacking >> Reclustering >> ... >> Rescheduling (Splitting, Packing, Scheduling, Unpacking) >> Assembly Printer >> >> >> In principle, it is possible to use the LLVM scheduler to generate parallel code by providing a custom hazard recognizer that checks true data dependencies of the cu...

...>>> ... >>> Clustering (Not required for unicluster VLIW architectures) >>> Scheduling >>> Packing >>> ... >>> Register Allocation >>> ... >>> Prolog/Epilog Insertion & Frame Finalization >>> Unpacking >>> Reclustering >>> ... >>> Rescheduling (Splitting, Packing, Scheduling, Unpacking) >>> Assembly Printer >>> >>> >>> In principle, it is possible to use the LLVM scheduler to generate parallel code by providing a custom hazard recognizer that checks true dat...

...gt; ... > >> Clustering (Not required for unicluster VLIW architectures) > >> Scheduling > >> Packing > >> ... > >> Register Allocation > >> ... > >> Prolog/Epilog Insertion & Frame Finalization > >> Unpacking > >> Reclustering > >> ... > >> Rescheduling (Splitting, Packing, Scheduling, Unpacking) > >> Assembly Printer > >> > >> > >> In principle, it is possible to use the LLVM scheduler to generate > parallel code by providing a custom hazard recognizer that chec...

...G->DAG Pattern Instruction Selection >> ... >> Clustering (Not required for unicluster VLIW architectures) >> Scheduling >> Packing >> ... >> Register Allocation >> ... >> Prolog/Epilog Insertion& Frame Finalization >> Unpacking >> Reclustering >> ... >> Rescheduling (Splitting, Packing, Scheduling, Unpacking) >> Assembly Printer >> >> >> In principle, it is possible to use the LLVM scheduler to generate parallel code by providing a custom hazard recognizer that checks true data dependencies of the curr...

...gt; ... > >> Clustering (Not required for unicluster VLIW architectures) > >> Scheduling > >> Packing > >> ... > >> Register Allocation > >> ... > >> Prolog/Epilog Insertion & Frame Finalization > >> Unpacking > >> Reclustering > >> ... > >> Rescheduling (Splitting, Packing, Scheduling, Unpacking) > >> Assembly Printer > >> > >> > >> In principle, it is possible to use the LLVM scheduler to generate > parallel code by providing a custom hazard recognizer that chec...

...>> DAG->DAG Pattern Instruction Selection >>> ... >>> Clustering (Not required for unicluster VLIW architectures) >>> Scheduling Packing ... >>> Register Allocation >>> ... >>> Prolog/Epilog Insertion & Frame Finalization Unpacking Reclustering >>> ... >>> Rescheduling (Splitting, Packing, Scheduling, Unpacking) Assembly >>> Printer >>> >>> >>> In principle, it is possible to use the LLVM scheduler to generate parallel code by providing a custom hazard recognizer that checks true d...

...ustering (Not required for unicluster VLIW architectures) >>>> Scheduling >>>> Packing >>>> ... >>>> Register Allocation >>>> ... >>>> Prolog/Epilog Insertion& Frame Finalization >>>> Unpacking >>>> Reclustering >>>> ... >>>> Rescheduling (Splitting, Packing, Scheduling, Unpacking) >>>> Assembly Printer >>>> >>>> >>>> In principle, it is possible to use the LLVM scheduler to generate >> parallel code by providing a custom hazard...

...tern Instruction Selection >>>> ... >>>> Clustering (Not required for unicluster VLIW architectures) >>>> Scheduling Packing ... >>>> Register Allocation >>>> ... >>>> Prolog/Epilog Insertion & Frame Finalization Unpacking Reclustering >>>> ... >>>> Rescheduling (Splitting, Packing, Scheduling, Unpacking) Assembly >>>> Printer >>>> >>>> >>>> In principle, it is possible to use the LLVM scheduler to generate parallel code by providing a custom hazard recog...

...tern Instruction Selection >>>> ... >>>> Clustering (Not required for unicluster VLIW architectures) >>>> Scheduling Packing ... >>>> Register Allocation >>>> ... >>>> Prolog/Epilog Insertion & Frame Finalization Unpacking Reclustering >>>> ... >>>> Rescheduling (Splitting, Packing, Scheduling, Unpacking) Assembly >>>> Printer >>>> >>>> >>>> In principle, it is possible to use the LLVM scheduler to generate parallel code by providing a custom hazard recog...

Dear R user, I am a biochemist/bioinformatician, at the moment working on protein clusterings by conformation similarity. I only started seriously working with R about a couple of months ago. I have been able so far to read my way through tutorials and set-up my hierarchical clusterings. My problem is that I cannot find a way to obtain information on the rooting of specific nodes, i.e. of