Displaying 16 results from an estimated 16 matches for "recluster".
Did you mean:
rcluster
2010 Jan 11
1
K-means recluster data with given cluster centers
K-means recluster data with given cluster centers
Dear R user,
I have several large data sets. Over time additional new data sets will be created.
I want to cluster all the data in a similar/ identical way with the k-means algorithm.
With the first data set I will find my cluster centers and save the cluster cent...
2011 Oct 21
0
[LLVMdev] VLIW Ports
...egister allocation.
I used the following pass order for the clustered VLIW back-end:
DAG->DAG Pattern Instruction Selection
...
Clustering (Not required for unicluster VLIW architectures)
Scheduling
Packing
...
Register Allocation
...
Prolog/Epilog Insertion & Frame Finalization
Unpacking
Reclustering
...
Rescheduling (Splitting, Packing, Scheduling, Unpacking)
Assembly Printer
In principle, it is possible to use the LLVM scheduler to generate parallel code by providing a custom hazard recognizer that checks true data dependencies of the current bundle. The scheduler has also the capability...
2011 Oct 22
3
[LLVMdev] VLIW Ports
...clustered VLIW back-end:
>
> DAG->DAG Pattern Instruction Selection
> ...
> Clustering (Not required for unicluster VLIW architectures)
> Scheduling
> Packing
> ...
> Register Allocation
> ...
> Prolog/Epilog Insertion & Frame Finalization
> Unpacking
> Reclustering
> ...
> Rescheduling (Splitting, Packing, Scheduling, Unpacking)
> Assembly Printer
>
>
> In principle, it is possible to use the LLVM scheduler to generate parallel code by providing a custom hazard recognizer that checks true data dependencies of the current bundle. The sch...
2011 Oct 06
3
[LLVMdev] VLIW Ports
Hi all,
here is the current (unfinished) version of the VLIW support I
mentioned. It is a patch over svn rev 141176. It includes the
MachineInstrBundle class, and small required changes in a couple of
outside LLVM files.
Also includes a modification to Mips target to simulate a 2-wide VLIW
MIPS. The scheduler is really silly, I did not want to implement a
scheduler, just the bundle class, and
2011 Oct 24
3
[LLVMdev] VLIW Ports
...clustered VLIW back-end:
>
> DAG->DAG Pattern Instruction Selection
> ...
> Clustering (Not required for unicluster VLIW architectures)
> Scheduling
> Packing
> ...
> Register Allocation
> ...
> Prolog/Epilog Insertion & Frame Finalization
> Unpacking
> Reclustering
> ...
> Rescheduling (Splitting, Packing, Scheduling, Unpacking)
> Assembly Printer
>
>
> In principle, it is possible to use the LLVM scheduler to generate parallel code by providing a custom hazard recognizer that checks true data dependencies of the current bundle. The sch...
2011 Oct 24
0
[LLVMdev] VLIW Ports
...->DAG Pattern Instruction Selection
>> ...
>> Clustering (Not required for unicluster VLIW architectures)
>> Scheduling
>> Packing
>> ...
>> Register Allocation
>> ...
>> Prolog/Epilog Insertion & Frame Finalization
>> Unpacking
>> Reclustering
>> ...
>> Rescheduling (Splitting, Packing, Scheduling, Unpacking)
>> Assembly Printer
>>
>>
>> In principle, it is possible to use the LLVM scheduler to generate parallel code by providing a custom hazard recognizer that checks true data dependencies of the...
2011 Oct 24
2
[LLVMdev] VLIW Ports
...->DAG Pattern Instruction Selection
>> ...
>> Clustering (Not required for unicluster VLIW architectures)
>> Scheduling
>> Packing
>> ...
>> Register Allocation
>> ...
>> Prolog/Epilog Insertion & Frame Finalization
>> Unpacking
>> Reclustering
>> ...
>> Rescheduling (Splitting, Packing, Scheduling, Unpacking)
>> Assembly Printer
>>
>>
>> In principle, it is possible to use the LLVM scheduler to generate
parallel code by providing a custom hazard recognizer that checks true data
dependencies of the...
2011 Oct 24
3
[LLVMdev] VLIW Ports
...>>> ...
>>> Clustering (Not required for unicluster VLIW architectures)
>>> Scheduling
>>> Packing
>>> ...
>>> Register Allocation
>>> ...
>>> Prolog/Epilog Insertion & Frame Finalization
>>> Unpacking
>>> Reclustering
>>> ...
>>> Rescheduling (Splitting, Packing, Scheduling, Unpacking)
>>> Assembly Printer
>>>
>>>
>>> In principle, it is possible to use the LLVM scheduler to generate parallel code by providing a custom hazard recognizer that checks true...
2011 Oct 25
0
[LLVMdev] VLIW Ports
...gt; ...
> >> Clustering (Not required for unicluster VLIW architectures)
> >> Scheduling
> >> Packing
> >> ...
> >> Register Allocation
> >> ...
> >> Prolog/Epilog Insertion & Frame Finalization
> >> Unpacking
> >> Reclustering
> >> ...
> >> Rescheduling (Splitting, Packing, Scheduling, Unpacking)
> >> Assembly Printer
> >>
> >>
> >> In principle, it is possible to use the LLVM scheduler to generate
> parallel code by providing a custom hazard recognizer that c...
2011 Oct 22
0
[LLVMdev] VLIW Ports
...G->DAG Pattern Instruction Selection
>> ...
>> Clustering (Not required for unicluster VLIW architectures)
>> Scheduling
>> Packing
>> ...
>> Register Allocation
>> ...
>> Prolog/Epilog Insertion& Frame Finalization
>> Unpacking
>> Reclustering
>> ...
>> Rescheduling (Splitting, Packing, Scheduling, Unpacking)
>> Assembly Printer
>>
>>
>> In principle, it is possible to use the LLVM scheduler to generate parallel code by providing a custom hazard recognizer that checks true data dependencies of the c...
2011 Oct 25
2
[LLVMdev] VLIW Ports
...gt; ...
> >> Clustering (Not required for unicluster VLIW architectures)
> >> Scheduling
> >> Packing
> >> ...
> >> Register Allocation
> >> ...
> >> Prolog/Epilog Insertion & Frame Finalization
> >> Unpacking
> >> Reclustering
> >> ...
> >> Rescheduling (Splitting, Packing, Scheduling, Unpacking)
> >> Assembly Printer
> >>
> >>
> >> In principle, it is possible to use the LLVM scheduler to generate
> parallel code by providing a custom hazard recognizer that c...
2011 Oct 25
0
[LLVMdev] VLIW Ports
...>> DAG->DAG Pattern Instruction Selection
>>> ...
>>> Clustering (Not required for unicluster VLIW architectures)
>>> Scheduling Packing ...
>>> Register Allocation
>>> ...
>>> Prolog/Epilog Insertion & Frame Finalization Unpacking Reclustering
>>> ...
>>> Rescheduling (Splitting, Packing, Scheduling, Unpacking) Assembly
>>> Printer
>>>
>>>
>>> In principle, it is possible to use the LLVM scheduler to generate parallel code by providing a custom hazard recognizer that checks tru...
2011 Oct 25
0
[LLVMdev] VLIW Ports
...ustering (Not required for unicluster VLIW architectures)
>>>> Scheduling
>>>> Packing
>>>> ...
>>>> Register Allocation
>>>> ...
>>>> Prolog/Epilog Insertion& Frame Finalization
>>>> Unpacking
>>>> Reclustering
>>>> ...
>>>> Rescheduling (Splitting, Packing, Scheduling, Unpacking)
>>>> Assembly Printer
>>>>
>>>>
>>>> In principle, it is possible to use the LLVM scheduler to generate
>> parallel code by providing a custom haza...
2011 Oct 26
2
[LLVMdev] VLIW Ports
...tern Instruction Selection
>>>> ...
>>>> Clustering (Not required for unicluster VLIW architectures)
>>>> Scheduling Packing ...
>>>> Register Allocation
>>>> ...
>>>> Prolog/Epilog Insertion & Frame Finalization Unpacking Reclustering
>>>> ...
>>>> Rescheduling (Splitting, Packing, Scheduling, Unpacking) Assembly
>>>> Printer
>>>>
>>>>
>>>> In principle, it is possible to use the LLVM scheduler to generate parallel code by providing a custom hazard re...
2011 Oct 26
0
[LLVMdev] VLIW Ports
...tern Instruction Selection
>>>> ...
>>>> Clustering (Not required for unicluster VLIW architectures)
>>>> Scheduling Packing ...
>>>> Register Allocation
>>>> ...
>>>> Prolog/Epilog Insertion & Frame Finalization Unpacking Reclustering
>>>> ...
>>>> Rescheduling (Splitting, Packing, Scheduling, Unpacking) Assembly
>>>> Printer
>>>>
>>>>
>>>> In principle, it is possible to use the LLVM scheduler to generate
parallel code by providing a custom hazard re...
2012 Feb 23
2
Advice on exploration of sub-clusters in hierarchical dendrogram
Dear R user,
I am a biochemist/bioinformatician, at the moment working on protein
clusterings by conformation similarity.
I only started seriously working with R about a couple of months ago.
I have been able so far to read my way through tutorials and set-up my
hierarchical clusterings. My problem is that I cannot find a way to obtain
information on the rooting of specific nodes, i.e. of