Displaying 4 results from an estimated 4 matches for "readonlyregclass".
2005 Jul 22
2
[LLVMdev] How to partition registers into different RegisterClass?
...egs
(read and write), and write-only regs. How should I partition them
into different RegisterClasses so that I can easy define the
instruction?
All RegisterClasses must be mutally exclusive. That is, a register can
only be in a RegisterClass. Otherwise TableGen will raise an error
message.
def ReadOnlyRegClass : RegisterClass<...>;
def GeneralPurposeRegClass : RegisterClass<...>;
def WriteOnlyRegClass : RegisterClass<...>;
def MOV : BinaryInst<2, (ops GeneralPurposeRegClass :$dest,
GeneralPurposeRegClass :$src), "mov $dest, $src">;
There can be only one RegisterC...
2005 Jul 22
0
[LLVMdev] How to partition registers into different RegisterClass?
...poseRegClass :$src), "mov $dest, $src">;
>
> There can be only one RegisterClass defined for each instruction
> operand, but actually the destition operand could be
> 'GeneralPurposeRegClass ' or 'WriteOnlyRegClass ', and the source
> operand can be 'ReadOnlyRegClass' or 'GeneralPurposeRegClass'.
Presumably, when you write your instruction selector, you know when you
want to have a write-only vs. general purpose and read-only vs. general
purpose register. Some things are naturally read-only, such as status
registers that are only modified as a sid...
2005 Jul 22
2
[LLVMdev] How to partition registers into different RegisterClass?
...ot;mov $dest, $src">;
> >
> > There can be only one RegisterClass defined for each instruction
> > operand, but actually the destition operand could be
> > 'GeneralPurposeRegClass ' or 'WriteOnlyRegClass ', and the source
> > operand can be 'ReadOnlyRegClass' or 'GeneralPurposeRegClass'.
>
> Presumably, when you write your instruction selector, you know when you
> want to have a write-only vs. general purpose and read-only vs. general
> purpose register. Some things are naturally read-only, such as status
> registers that a...
2005 Jul 22
0
[LLVMdev] How to partition registers into different RegisterClass?
...src">;
>>>
>>> There can be only one RegisterClass defined for each instruction
>>> operand, but actually the destition operand could be
>>> 'GeneralPurposeRegClass ' or 'WriteOnlyRegClass ', and the source
>>> operand can be 'ReadOnlyRegClass' or 'GeneralPurposeRegClass'.
>>
>> Presumably, when you write your instruction selector, you know when you
>> want to have a write-only vs. general purpose and read-only vs. general
>> purpose register. Some things are naturally read-only, such as status
>&g...