Displaying 3 results from an estimated 3 matches for "readim".
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radim
2018 Nov 15
2
Per-write cycle count with ReadAdvance - Do I really need that?
...roc)ReadAdvance to be a list of int and 2) changing tablegen to allow
multiple (Proc)ReadAdvance records with the same read resource.
The former solution doesn't seem ideal as it requires repeating the
cycle count many times for targets that use long SchedWriteRes lists:
-def : ReadAdvance<ReadIM, 1, [WriteImm,WriteI,
+def: ReadAdvance<ReadIM, [1, 1, 1, 1, 1, 1, 1, 1], [WriteImm, WriteI,
WriteISReg, WriteIEReg,WriteIS,
WriteID32,WriteID64,
WriteIM32,WriteIM64]>;
The latter is a bit more ve...
2018 Nov 17
2
Per-write cycle count with ReadAdvance - Do I really need that?
...of int and 2) changing tablegen to allow
> multiple (Proc)ReadAdvance records with the same read resource.
>
> The former solution doesn't seem ideal as it requires repeating the
> cycle count many times for targets that use long SchedWriteRes lists:
>
> -def : ReadAdvance<ReadIM, 1, [WriteImm,WriteI,
> +def: ReadAdvance<ReadIM, [1, 1, 1, 1, 1, 1, 1, 1], [WriteImm, WriteI,
> WriteISReg, WriteIEReg,WriteIS,
> WriteID32,WriteID64,
> WriteIM32,WriteIM64]>;
>
>...
2018 Nov 19
2
Per-write cycle count with ReadAdvance - Do I really need that?
...tablegen to allow
>> multiple (Proc)ReadAdvance records with the same read resource.
>>
>> The former solution doesn't seem ideal as it requires repeating the
>> cycle count many times for targets that use long SchedWriteRes lists:
>>
>> -def : ReadAdvance<ReadIM, 1, [WriteImm,WriteI,
>> +def: ReadAdvance<ReadIM, [1, 1, 1, 1, 1, 1, 1, 1], [WriteImm, WriteI,
>> WriteISReg, WriteIEReg,WriteIS,
>> WriteID32,WriteID64,
>> WriteIM32,WriteIM6...