Displaying 6 results from an estimated 6 matches for "read_vco".
Did you mean:
read_cb
2016 Jun 04
0
[PATCH 2/3] nvkm/clk/gf100: Read secondary bypass postdiv when required
...4));
- u32 sctl = nvkm_rd32(device, dctl + (doff * 4));
+ u32 sclk, sctl, sdiv = 2;
switch (ssrc & 0x00000003) {
case 0:
@@ -109,13 +109,21 @@ read_div(struct gf100_clk *clk, int doff, u32 dsrc, u32 dctl)
case 2:
return 100000;
case 3:
- if (sctl & 0x80000000) {
- u32 sclk = read_vco(clk, dsrc + (doff * 4));
- u32 sdiv = (sctl & 0x0000003f) + 2;
- return (sclk * 2) / sdiv;
+ sclk = read_vco(clk, dsrc + (doff * 4));
+
+ /* Memclk has doff of 0 despite it's alt. location */
+ if (doff <= 2) {
+ sctl = nvkm_rd32(device, dctl + (doff * 4));
+
+ if (sctl &...
2016 Jun 17
0
[PATCH v2 2/2] nvkm/clk/gf100: Read secondary bypass postdiv when required
...4));
- u32 sctl = nvkm_rd32(device, dctl + (doff * 4));
+ u32 sclk, sctl, sdiv = 2;
switch (ssrc & 0x00000003) {
case 0:
@@ -109,13 +109,21 @@ read_div(struct gf100_clk *clk, int doff, u32 dsrc, u32 dctl)
case 2:
return 100000;
case 3:
- if (sctl & 0x80000000) {
- u32 sclk = read_vco(clk, dsrc + (doff * 4));
- u32 sdiv = (sctl & 0x0000003f) + 2;
- return (sclk * 2) / sdiv;
+ sclk = read_vco(clk, dsrc + (doff * 4));
+
+ /* Memclk has doff of 0 despite its alt. location */
+ if (doff <= 2) {
+ sctl = nvkm_rd32(device, dctl + (doff * 4));
+
+ if (sctl & 0x800...
2016 Jun 17
1
[PATCH v2 1/2] nvkm/clk/gf100+: Clean up PLL locking test
Corresponds with GT215. Don't rely on the lock test logic being unconditionally
enabled, and disable test logic when done (presumably to save power).
v2: Remove warning, nvkm_msec already warns on time-out
Signed-off-by: Roy Spliet <nouveau at spliet.org>
---
drivers/gpu/drm/nouveau/nvkm/subdev/clk/gf100.c | 8 +++++++-
drivers/gpu/drm/nouveau/nvkm/subdev/clk/gk104.c | 8 +++++++-
2
2016 Jun 04
3
PM + Init work
Following a series of three patches, two of which have been sitting in my tree
for a while, the third is the result of some inspection of an NV134 BIOS that
seems to use the 0xaf upcode to upload training patterns. Please test!
Roy
Ps. Sorry they come from yet another e-mail address. My previous provider,
eclipso, actively blocks users of git send-email. Inquiries fall on deaf
ears, hence I
2014 Aug 21
9
NVA3 clock tree improvements
Following a series of patches to improve nouveaus clock tree parsing. Reclocking these engines (all but memory) is pretty stable on the cards I've tested. Please review and merge when approved.
These patches do not solve the problem that core/shader engine doesn't like to be clocked up too far without fb following, with visible corruption as a result. I suspect this problem is unrelated
2014 Aug 21
0
[PATCH 2/7] clock/nva3: Set PLL refclk
...uct nvbios_pll limits;
- u32 oclk, sclk, sdiv;
- int P, N, M, diff;
- int ret;
+ u32 oclk, sclk, sdiv, diff;
- info->pll = 0;
info->clk = 0;
switch (khz) {
@@ -188,40 +183,64 @@ nva3_clock_info(struct nouveau_clock *clock, int clk, u32 pll, u32 khz,
return khz;
default:
sclk = read_vco(priv, clk);
- sdiv = min((sclk * 2) / (khz - 2999), (u32)65);
- /* if the clock has a PLL attached, and we can get a within
- * [-2, 3) MHz of a divider, we'll disable the PLL and use
- * the divider instead.
- *
- * divider can go as low as 2, limited here because NVIDIA
+ sdiv = mi...