Displaying 13 results from an estimated 13 matches for "read_div".
2016 Jun 04
0
[PATCH 2/3] nvkm/clk/gf100: Read secondary bypass postdiv when required
...4 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/clk/gf100.c b/drivers/gpu/drm/nouveau/nvkm/subdev/clk/gf100.c
index f9a4918..80c6dd6 100644
--- a/drivers/gpu/drm/nouveau/nvkm/subdev/clk/gf100.c
+++ b/drivers/gpu/drm/nouveau/nvkm/subdev/clk/gf100.c
@@ -99,7 +99,7 @@ read_div(struct gf100_clk *clk, int doff, u32 dsrc, u32 dctl)
{
struct nvkm_device *device = clk->base.subdev.device;
u32 ssrc = nvkm_rd32(device, dsrc + (doff * 4));
- u32 sctl = nvkm_rd32(device, dctl + (doff * 4));
+ u32 sclk, sctl, sdiv = 2;
switch (ssrc & 0x00000003) {
case 0:
@@ -109...
2016 Jun 17
0
[PATCH v2 2/2] nvkm/clk/gf100: Read secondary bypass postdiv when required
...4 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/clk/gf100.c b/drivers/gpu/drm/nouveau/nvkm/subdev/clk/gf100.c
index 026baff..89d5543 100644
--- a/drivers/gpu/drm/nouveau/nvkm/subdev/clk/gf100.c
+++ b/drivers/gpu/drm/nouveau/nvkm/subdev/clk/gf100.c
@@ -99,7 +99,7 @@ read_div(struct gf100_clk *clk, int doff, u32 dsrc, u32 dctl)
{
struct nvkm_device *device = clk->base.subdev.device;
u32 ssrc = nvkm_rd32(device, dsrc + (doff * 4));
- u32 sctl = nvkm_rd32(device, dctl + (doff * 4));
+ u32 sclk, sctl, sdiv = 2;
switch (ssrc & 0x00000003) {
case 0:
@@ -109...
2016 Jun 17
1
[PATCH v2 1/2] nvkm/clk/gf100+: Clean up PLL locking test
Corresponds with GT215. Don't rely on the lock test logic being unconditionally
enabled, and disable test logic when done (presumably to save power).
v2: Remove warning, nvkm_msec already warns on time-out
Signed-off-by: Roy Spliet <nouveau at spliet.org>
---
drivers/gpu/drm/nouveau/nvkm/subdev/clk/gf100.c | 8 +++++++-
drivers/gpu/drm/nouveau/nvkm/subdev/clk/gk104.c | 8 +++++++-
2
2016 Jun 04
3
PM + Init work
Following a series of three patches, two of which have been sitting in my tree
for a while, the third is the result of some inspection of an NV134 BIOS that
seems to use the 0xaf upcode to upload training patterns. Please test!
Roy
Ps. Sorry they come from yet another e-mail address. My previous provider,
eclipso, actively blocks users of git send-email. Inquiries fall on deaf
ears, hence I
2013 Dec 06
2
Regression: drm/nouveau/clk: implement power state and engine clock control in core (7c856522069755ab9d163a24ac332cd3cb35fe30) breaks GeForce 9400 on Intel Mac Mini Model November 2010 model
...ubdev/clock/nvaa.o
drivers/gpu/drm/nouveau/core/subdev/clock/nvaa.c:478:8: error: redefinition of 'struct nvaa_clock_priv'
drivers/gpu/drm/nouveau/core/subdev/clock/nvaa.c:33:8: note: originally defined here
drivers/gpu/drm/nouveau/core/subdev/clock/nvaa.c:488:1: error: redefinition of 'read_div'
drivers/gpu/drm/nouveau/core/subdev/clock/nvaa.c:43:1: note: previous definition of 'read_div' was here
drivers/gpu/drm/nouveau/core/subdev/clock/nvaa.c:494:1: error: redefinition of 'read_pll'
drivers/gpu/drm/nouveau/core/subdev/clock/nvaa.c:49:1: note: previous definition of...
2013 Dec 06
0
Regression: drm/nouveau/clk: implement power state and engine clock control in core (7c856522069755ab9d163a24ac332cd3cb35fe30) breaks GeForce 9400 on Intel Mac Mini Model November 2010 model
...u sure you applied the patch
correctly? The file should only be 445 lines long, I'm guessing you
double-applied it?
> drivers/gpu/drm/nouveau/core/subdev/clock/nvaa.c:33:8: note: originally defined here
> drivers/gpu/drm/nouveau/core/subdev/clock/nvaa.c:488:1: error: redefinition of 'read_div'
> drivers/gpu/drm/nouveau/core/subdev/clock/nvaa.c:43:1: note: previous definition of 'read_div' was here
> drivers/gpu/drm/nouveau/core/subdev/clock/nvaa.c:494:1: error: redefinition of 'read_pll'
> drivers/gpu/drm/nouveau/core/subdev/clock/nvaa.c:49:1: note: previous...
2013 Nov 16
0
[PATCH] drm/nouveau/clk: Implement reclocking for NVAA/NVAC
...ER DEALINGS IN THE SOFTWARE.
+ *
+ * Authors: Ben Skeggs
+ */
+
+#include <engine/fifo.h>
+#include <subdev/bios.h>
+#include <subdev/bios/pll.h>
+#include <subdev/timer.h>
+
+#include "nv50.h"
+#include "nvaa.h"
+#include "pll.h"
+
+static u32
+read_div(struct nouveau_clock *clk)
+{
+ return nv_rd32(clk, 0x004600);
+}
+
+static u32
+read_pll(struct nouveau_clock *clk, u32 base)
+{
+ u32 ctrl = nv_rd32(clk, base + 0);
+ u32 coef = nv_rd32(clk, base + 4);
+ u32 ref = clk->read(clk, nv_clk_src_href);
+ u32 post_div = 0;
+ u32 clock = 0;
+ int N1,...
2013 Nov 17
0
[PATCH] drm/nouveau/clk: Implement reclocking for NVAA/NVAC
...ER DEALINGS IN THE SOFTWARE.
+ *
+ * Authors: Ben Skeggs
+ */
+
+#include <engine/fifo.h>
+#include <subdev/bios.h>
+#include <subdev/bios/pll.h>
+#include <subdev/timer.h>
+
+#include "nv50.h"
+#include "nvaa.h"
+#include "pll.h"
+
+static u32
+read_div(struct nouveau_clock *clk)
+{
+ return nv_rd32(clk, 0x004600);
+}
+
+static u32
+read_pll(struct nouveau_clock *clk, u32 base)
+{
+ u32 ctrl = nv_rd32(clk, base + 0);
+ u32 coef = nv_rd32(clk, base + 4);
+ u32 ref = clk->read(clk, nv_clk_src_href);
+ u32 post_div = 0;
+ u32 clock = 0;
+ int N1,...
2020 Oct 19
2
[PATCH] drm: remove unneeded break
...7..4884eb4a9221 100644
--- a/drivers/gpu/drm/nouveau/nvkm/subdev/clk/mcp77.c
+++ b/drivers/gpu/drm/nouveau/nvkm/subdev/clk/mcp77.c
@@ -140,17 +140,14 @@ mcp77_clk_read(struct nvkm_clk *base, enum nv_clk_src src)
break;
case nv_clk_src_mem:
return 0;
- break;
case nv_clk_src_vdec:
P = (read_div(clk) & 0x00000700) >> 8;
switch (mast & 0x00400000) {
case 0x00400000:
return nvkm_clk_read(&clk->base, nv_clk_src_core) >> P;
- break;
default:
return 500000 >> P;
- break;
}
break;
default:
diff --git a/drivers/gpu/drm/nouveau/nvkm/s...
2013 Nov 09
2
[PATCH] drm/nouveau/clk: Initial implementation for reclocking NVAA/NVAC
Reclocking of NVAA/NVAC is substantially different from NV50+, enough to justify a separate clock implementation. This code is a forward-port of reclocking code that has been sitting in a branch for a while, and has been tested on my NVAC. Traces show no significant reasons why this shouldn't work on NVAA, but testers are always welcome. And since these are IGPs without dedicated RAM to
2013 Dec 06
2
Regression: drm/nouveau/clk: implement power state and engine clock control in core (7c856522069755ab9d163a24ac332cd3cb35fe30) breaks GeForce 9400 on Intel Mac Mini Model November 2010 model
Hello everyone,
the current git HEAD of Linus Torvalds tree breaks Nouveau on my Mac Mini
Model 2010. I get variation of the following kernel panic when booting.
(gateway) [~] nc -u -l -p 6666
[ 3.796018] ata1: SATA link up 3.0 Gbps (SStatus 123 SControl 300)
[ 3.796100] ata2: SATA link up 1.5 Gbps (SStatus 113 SControl 300)
[ 3.796304] ata1.00: ATA-7: INTEL SSDSA2M160G2GC, 2CV102HA, max
2020 Oct 17
10
[RFC] treewide: cleanup unreachable breaks
.../mcp77.c
+++ b/drivers/gpu/drm/nouveau/nvkm/subdev/clk/mcp77.c
@@ -138,21 +138,18 @@ mcp77_clk_read(struct nvkm_clk *base, enum nv_clk_src src)
case 0x00000030: return read_pll(clk, 0x004020) >> P;
}
break;
case nv_clk_src_mem:
return 0;
- break;
case nv_clk_src_vdec:
P = (read_div(clk) & 0x00000700) >> 8;
switch (mast & 0x00400000) {
case 0x00400000:
return nvkm_clk_read(&clk->base, nv_clk_src_core) >> P;
- break;
default:
return 500000 >> P;
- break;
}
break;
default:
break;
}
diff --git a/drivers/gpu/drm/...
2020 Oct 17
10
[RFC] treewide: cleanup unreachable breaks
.../mcp77.c
+++ b/drivers/gpu/drm/nouveau/nvkm/subdev/clk/mcp77.c
@@ -138,21 +138,18 @@ mcp77_clk_read(struct nvkm_clk *base, enum nv_clk_src src)
case 0x00000030: return read_pll(clk, 0x004020) >> P;
}
break;
case nv_clk_src_mem:
return 0;
- break;
case nv_clk_src_vdec:
P = (read_div(clk) & 0x00000700) >> 8;
switch (mast & 0x00400000) {
case 0x00400000:
return nvkm_clk_read(&clk->base, nv_clk_src_core) >> P;
- break;
default:
return 500000 >> P;
- break;
}
break;
default:
break;
}
diff --git a/drivers/gpu/drm/...