Displaying 7 results from an estimated 7 matches for "read_clk".
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read_blk
2017 Sep 06
2
[PATCH] [RESEND] drm/nouveau/clk: fix gcc-7 -Wint-in-bool-context warning
.../subdev/clk/gt215.c b/drivers/gpu/drm/nouveau/nvkm/subdev/clk/gt215.c
index 96e0941c8edd..04b4f4ccf186 100644
--- a/drivers/gpu/drm/nouveau/nvkm/subdev/clk/gt215.c
+++ b/drivers/gpu/drm/nouveau/nvkm/subdev/clk/gt215.c
@@ -130,10 +130,10 @@ read_pll(struct gt215_clk *clk, int idx, u32 pll)
sclk = read_clk(clk, 0x10 + idx, false);
}
- if (M * P)
- return sclk * N / (M * P);
+ if (M * P == 0)
+ return 0;
- return 0;
+ return sclk * N / (M * P);
}
static int
--
2.9.0
2014 Aug 21
9
NVA3 clock tree improvements
Following a series of patches to improve nouveaus clock tree parsing. Reclocking these engines (all but memory) is pretty stable on the cards I've tested. Please review and merge when approved.
These patches do not solve the problem that core/shader engine doesn't like to be clocked up too far without fb following, with visible corruption as a result. I suspect this problem is unrelated
2017 Jul 14
0
[PATCH 12/14] drm/nouveau/clk: fix gcc-7 -Wint-in-bool-context warning
.../subdev/clk/gt215.c b/drivers/gpu/drm/nouveau/nvkm/subdev/clk/gt215.c
index 96e0941c8edd..04b4f4ccf186 100644
--- a/drivers/gpu/drm/nouveau/nvkm/subdev/clk/gt215.c
+++ b/drivers/gpu/drm/nouveau/nvkm/subdev/clk/gt215.c
@@ -130,10 +130,10 @@ read_pll(struct gt215_clk *clk, int idx, u32 pll)
sclk = read_clk(clk, 0x10 + idx, false);
}
- if (M * P)
- return sclk * N / (M * P);
+ if (M * P == 0)
+ return 0;
- return 0;
+ return sclk * N / (M * P);
}
static int
--
2.9.0
2017 Sep 06
0
[PATCH] [RESEND] drm/nouveau/clk: fix gcc-7 -Wint-in-bool-context warning
...nouveau/nvkm/subdev/clk/gt215.c
> index 96e0941c8edd..04b4f4ccf186 100644
> --- a/drivers/gpu/drm/nouveau/nvkm/subdev/clk/gt215.c
> +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/clk/gt215.c
> @@ -130,10 +130,10 @@ read_pll(struct gt215_clk *clk, int idx, u32 pll)
> sclk = read_clk(clk, 0x10 + idx, false);
> }
>
> - if (M * P)
> - return sclk * N / (M * P);
> + if (M * P == 0)
> + return 0;
>
> - return 0;
> + return sclk * N / (M * P);
> }
>
> static int
> --
> 2.9.0
>...
2017 Sep 06
0
[PATCH] [v2] drm/nouveau/clk: fix gcc-7 -Wint-in-bool-context warning
...l)
struct nvkm_device *device = clk->base.subdev.device;
u32 ctrl = nvkm_rd32(device, pll + 0);
u32 sclk = 0, P = 1, N = 1, M = 1;
+ u32 MP;
if (!(ctrl & 0x00000008)) {
if (ctrl & 0x00000001) {
@@ -130,10 +131,12 @@ read_pll(struct gt215_clk *clk, int idx, u32 pll)
sclk = read_clk(clk, 0x10 + idx, false);
}
- if (M * P)
- return sclk * N / (M * P);
+ MP = M * P;
- return 0;
+ if (!MP)
+ return 0;
+
+ return sclk * N / MP;
}
static int
--
2.9.0
2018 Jan 16
0
[PATCH] [RESEND v2] drm/nouveau/clk: fix gcc-7 -Wint-in-bool-context warning
...l)
struct nvkm_device *device = clk->base.subdev.device;
u32 ctrl = nvkm_rd32(device, pll + 0);
u32 sclk = 0, P = 1, N = 1, M = 1;
+ u32 MP;
if (!(ctrl & 0x00000008)) {
if (ctrl & 0x00000001) {
@@ -130,10 +131,12 @@ read_pll(struct gt215_clk *clk, int idx, u32 pll)
sclk = read_clk(clk, 0x10 + idx, false);
}
- if (M * P)
- return sclk * N / (M * P);
+ MP = M * P;
- return 0;
+ if (!MP)
+ return 0;
+
+ return sclk * N / MP;
}
static int
--
2.9.0
2014 Aug 21
0
[PATCH 2/7] clock/nva3: Set PLL refclk
...e divider instead. */
+ clk_khz = nva3_clk_info(clock, clk, khz, info);
+ diff = khz - clk_khz;
+ if (!pll || (diff >= -2000 && diff < 3000)) {
+ return clk_khz;
+ }
+
+ /* Try with PLL */
ret = nvbios_pll_parse(bios, pll, &limits);
if (ret)
return ret;
- limits.refclk = read_clk(priv, clk - 0x10, true);
- if (!limits.refclk)
+ clk_khz = nva3_clk_info(clock, clk - 0x10, limits.refclk, info);
+ if (clk_khz != limits.refclk)
return -EINVAL;
ret = nva3_pll_calc(nv_subdev(priv), &limits, khz, &N, NULL, &M, &P);
if (ret >= 0) {
- info->clk = nv_rd...