search for: rdst

...t(struct nv50_pc *pc, unsigned c_op, struct nv50_reg *dst, +emit_set(struct nv50_pc *pc, unsigned ccode, struct nv50_reg *dst, int wp, struct nv50_reg *src0, struct nv50_reg *src1) { struct nv50_program_exec *e = exec(pc); - unsigned inv_cop[8] = { 0, 4, 2, 6, 1, 5, 3, 7 }; struct nv50_reg *rdst; - assert(c_op <= 7); + assert(ccode < 16); if (check_swap_src_0_1(pc, &src0, &src1)) - c_op = inv_cop[c_op]; + ccode = ccode ^ 0x7; rdst = dst; - if (dst->type != P_TEMP) + if (dst && dst->type != P_TEMP) dst = alloc_temp(pc, NULL); /* set.u32 */ set_...

...et(struct nv50_pc *pc, unsigned c_op, struct nv50_reg *dst, +emit_set(struct nv50_pc *pc, unsigned c_op, struct nv50_reg *dst, int wp, struct nv50_reg *src0, struct nv50_reg *src1) { struct nv50_program_exec *e = exec(pc); - unsigned inv_cop[8] = { 0, 4, 2, 6, 1, 5, 3, 7 }; struct nv50_reg *rdst; - assert(c_op <= 7); if (check_swap_src_0_1(pc, &src0, &src1)) - c_op = inv_cop[c_op]; + c_op += 8; rdst = dst; - if (dst->type != P_TEMP) - dst = alloc_temp(pc, NULL); + if (dst && dst->type != P_TEMP) + dst = temp_temp(pc); /* set.u32 */ set_long(pc, e)...

...a/src/gallium/drivers/nv50/nv50_program.c +++ b/src/gallium/drivers/nv50/nv50_program.c @@ -1294,18 +1294,20 @@ static boolean nv50_program_tx_insn(struct nv50_pc *pc, const union tgsi_full_token *tok) { const struct tgsi_full_instruction *inst = &tok->FullInstruction; - struct nv50_reg *rdst[4], *dst[4], *src[3][4], *temp; - unsigned mask, sat, unit; + struct nv50_reg *rdst[4], *dst[4], *src[3][4]; + struct nv50_reg **pp_rtmp, *rtmp = NULL, *temp = NULL; + unsigned mask, sat, unit = 0; boolean assimilate = FALSE; - int i, c; + int i, c, nr_dst = 0; mask = inst->FullDstRegister...

...ita On Sun, Jun 4, 2017 at 8:22 PM, Sean Silva <chisophugis at gmail.com> wrote: > I'm having a hard time grasping what this ISA actually looks like. > > When you say that it has a single instruction that is a majority function, > I assume something like this: > > MAJ rDst <- rSrc0, rSrc1, rSrc2 > Semantics: > for (int i = 0; i < REGISTER_WIDTH; i++) { > rDst[i] = maj(rSrc0[i], rSrc1[i], rSrc2[i]); > } > Where maj(a, b, c) = (a & b) | (a & c) | (b & c) > > But that doesn't make sense given your question. > > MAJ is a...

Hello everyone, I was trying to create an LLVM backend for a processor with a very simple architecture and that does all instructions like load, store, arithmetic and logical instructions using a bunch of majority functions. The processor has only one instruction(majority function) in its ISA and breaks down all other instructions into a number of majority instructions depending on what

...he end of each output as demonstrated below. How can I generate this (and similar) result(s) without all the trailing NULLs? > lapply(ls(pattern='bn'), function(x) cat(x, dim(get(x)), "\t", names(get(x)), "\n")) bn1993 2885 11 oplt rplt rsiz tree bd ht oaz odst raz rdst spr bn1994 3158 7 oplt tree bd ht spr stat dam bn1995 734 7 oplt tree bd ht spr stat dam bn1996 293 7 oplt tree bd ht spr stat dam bn1997 264 7 oplt tree bd ht spr stat dam bn1998 768 7 oplt tree bd ht spr stat dam bn1999 654 7 oplt tree bd ht dbh stat dam bn2003 1407...

This comse from iproute-ss050901, rebuilt on FC4 with -fortify-source option. Seems like ip has a buffer overflow which sometimes causes a segfault.. will try to look at it tmrw, so far here''s my gdb output. $ gdb ip GNU gdb Red Hat Linux (6.3.0.0-1.21rh) Copyright 2004 Free Software Foundation, Inc. GDB is free software, covered by the GNU General Public License, and you are welcome

...= 0; c < 4; ++c) { > if (!dst0[c]) > continue; > @@ -2489,10 +2504,12 @@ Converter::handleATOM(Value *dst0[4], DataType ty, uint16_t subOp) > for (int c = 0; c < 4; ++c) > if (dst0[c]) > dst0[c] = dst; // not equal to rDst so handleInstruction will do mkMov > - return; > + break; > + default: > + assert(!"Unsupported srcFile for ATOM"); > } > > - > +/* Keep this around for now as reference when adding img support > getResourceCoords(srcv, r, 1); > &gt...

...+ case TGSI_OPCODE_KIL: + /* don't call this function for these ops */ + assert(0); + break; default: - return TRUE; + /* linear vector instruction */ + return (1 << c); } } @@ -1393,25 +1432,6 @@ nv50_program_tx_insn(struct nv50_pc *pc, const union tgsi_full_token *tok) rdst[c] = dst[c]; dst[c] = temp_temp(pc); } - } else - if (direct2dest_op(inst)) { - for (c = 0; c < 4; c++) { - if (!dst[c] || dst[c]->type != P_TEMP) - continue; - - for (i = c + 1; i < 4; i++) { - if (dst[c] == src[0][i] || - dst[c] == src[1][i] || - dst[c] ==...

Hi ! I've been trying to improve NV50 shader generation a bit the last couple of weeks, so here is what I've produced. I don't know if it's usable for you or just a pile of horrible hacks, but at least it makes some mesa demos render more correcly, p.e. the teapot (aside from mip-mapping issues of the floor texture), arbfplight, and I think the gears also didn't appear as they

...GSI_FILE_MEMORY: for (int c = 0; c < 4; ++c) { if (!dst0[c]) continue; @@ -2489,10 +2504,12 @@ Converter::handleATOM(Value *dst0[4], DataType ty, uint16_t subOp) for (int c = 0; c < 4; ++c) if (dst0[c]) dst0[c] = dst; // not equal to rDst so handleInstruction will do mkMov - return; + break; + default: + assert(!"Unsupported srcFile for ATOM"); } - +/* Keep this around for now as reference when adding img support getResourceCoords(srcv, r, 1); if (isResourceSpecial(r)) { @@ -2520,6 +2537,7...

...for now as reference when adding img support getResourceCoords(srcv, r, 1); if (isResourceSpecial(r)) { @@ -2512,6 +2520,7 @@ Converter::handleATOM(Value *dst0[4], DataType ty, uint16_t subOp) for (int c = 0; c < 4; ++c) if (dst0[c]) dst0[c] = dst; // not equal to rDst so handleInstruction will do mkMov +*/ } void -- 2.7.2

...t;> if (!dst0[c]) >> continue; >> @@ -2489,10 +2504,12 @@ Converter::handleATOM(Value *dst0[4], DataType ty, uint16_t subOp) >> for (int c = 0; c < 4; ++c) >> if (dst0[c]) >> dst0[c] = dst; // not equal to rDst so handleInstruction will do mkMov >> - return; >> + break; >> + default: >> + assert(!"Unsupported srcFile for ATOM"); >> } >> >> - >> +/* Keep this around for now as reference when adding img support >> get...

...->hw; + + FREE(src); +} + static boolean check_swap_src_0_1(struct nv50_pc *pc, struct nv50_reg **s0, struct nv50_reg **s1) @@ -866,6 +885,8 @@ emit_set(struct nv50_pc *pc, unsigned c_op, struct nv50_reg *dst, set_src_0(pc, dst, e); emit(pc, e); + pc->if_cond = e; + if (dst != rdst) free_temp(pc, dst); } @@ -1098,6 +1119,39 @@ emit_tex(struct nv50_pc *pc, struct nv50_reg **dst, unsigned mask, } static void +emit_branch(struct nv50_pc *pc, int pred, unsigned cc, void *join) +{ + struct nv50_program_exec *e = exec(pc); + + if (join) { + set_long(pc, e); + e->inst[0...

tgsi_default_instruction_memory / tgsi_build_instruction_memory were returning uninitialized memory for tgsi_instruction_memory.Texture and tgsi_instruction_memory.Format. Note 0 means not set, and thus is a correct default initializer for these. Fixes: 3243b6fc97 ("tgsi: add Texture and Format to tgsi_instruction_memory") Cc: Nicolai Hähnle <nicolai.haehnle at amd.com>