search for: rdpmc

I want to measure the performance of a JITed code snippet on MCJIT. so I was planning to inject the RDPMC inst for the code generated through a llvm IR builder. Is there a patch available ? If there's a better way to do it please chime in. Thanks sathvik -------------- next part -------------- An HTML attachment was scrubbed... URL: <http://lists.llvm.org/pipermail/llvm-dev/attachments/2014061...

..."=d" (high)) - -#define rdtscl(low) \ - __asm__ __volatile__("rdtsc" : "=a" (low) : : "edx") - -#define rdtscll(val) \ - __asm__ __volatile__("rdtsc" : "=A" (val)) - -#define write_tsc(val1,val2) wrmsr(0x10, val1, val2) - -#define rdpmc(counter,low,high) \ - __asm__ __volatile__("rdpmc" \ - : "=a" (low), "=d" (high) \ - : "c" (counter)) - /* symbolic names for some interesting MSRs */ /* Intel defined MSRs. */ #define MSR_IA32_P5_MC_ADDR 0 Index: linux-2.6.16-rc5/include/asm-...

..."=d" (high)) - -#define rdtscl(low) \ - __asm__ __volatile__("rdtsc" : "=a" (low) : : "edx") - -#define rdtscll(val) \ - __asm__ __volatile__("rdtsc" : "=A" (val)) - -#define write_tsc(val1,val2) wrmsr(0x10, val1, val2) - -#define rdpmc(counter,low,high) \ - __asm__ __volatile__("rdpmc" \ - : "=a" (low), "=d" (high) \ - : "c" (counter)) - /* symbolic names for some interesting MSRs */ /* Intel defined MSRs. */ #define MSR_IA32_P5_MC_ADDR 0 Index: linux-2.6.16-rc5/include/asm-...

Hello, This series of patches integrates msr.h header. What it really does, is a series of steps to allow us to get rid of duplicate code between i386 and x86_64 versions With this done, achieving paravirt for x86_64 gets really easy, just a couple of extra code. The first patch was already sent a while ago, but was not yet pushed to any tree , to my knowledge. So it is sent again. Also,

Hello, This series of patches integrates msr.h header. What it really does, is a series of steps to allow us to get rid of duplicate code between i386 and x86_64 versions With this done, achieving paravirt for x86_64 gets really easy, just a couple of extra code. The first patch was already sent a while ago, but was not yet pushed to any tree , to my knowledge. So it is sent again. Also,

...- asm volatile (".byte 0x0f,0x01,0xf9" : "=a" (low), "=d" (high), "=c" (aux)) #define rdtscll(val) do { \ unsigned int __a,__d; \ @@ -75,42 +110,43 @@ (val) = ((unsigned long)__a) | (((unsigned long)__d)<<32); \ } while(0) +#define rdpmc(counter,low,high) \ + __asm__ __volatile__("rdpmc" \ + : "=a" (low), "=d" (high) \ + : "c" (counter)) + +#define rdtscp(low,high,aux) \ + asm volatile (".byte 0x0f,0x01,0xf9" : "=a" (low), "=d" (high), "=c&qu...

...- asm volatile (".byte 0x0f,0x01,0xf9" : "=a" (low), "=d" (high), "=c" (aux)) #define rdtscll(val) do { \ unsigned int __a,__d; \ @@ -75,42 +110,43 @@ (val) = ((unsigned long)__a) | (((unsigned long)__d)<<32); \ } while(0) +#define rdpmc(counter,low,high) \ + __asm__ __volatile__("rdpmc" \ + : "=a" (low), "=d" (high) \ + : "c" (counter)) + +#define rdtscp(low,high,aux) \ + asm volatile (".byte 0x0f,0x01,0xf9" : "=a" (low), "=d" (high), "=c&qu...

On Sat, Apr 25, 2020 at 5:49 AM Joerg Roedel <jroedel at suse.de> wrote: > > Hi Dave, > > On Fri, Apr 24, 2020 at 03:53:09PM -0700, Dave Hansen wrote: > > Ahh, so any instruction that can have an instruction intercept set > > potentially needs to be able to tolerate a #VC? Those instruction > > intercepts are under the control of the (untrusted relative to the

On Sat, Apr 25, 2020 at 5:49 AM Joerg Roedel <jroedel at suse.de> wrote: > > Hi Dave, > > On Fri, Apr 24, 2020 at 03:53:09PM -0700, Dave Hansen wrote: > > Ahh, so any instruction that can have an instruction intercept set > > potentially needs to be able to tolerate a #VC? Those instruction > > intercepts are under the control of the (untrusted relative to the

...have some questions about them: "Add support for 16-bit x86 assembly and real mode to the assembler and disassembler, for use by BIOS code. This includes both 16-bit instruction encodings as well as privileged instructions (lgdt, lldt, ltr, lmsw, clts, invd, invlpg, wbinvd, hlt, rdmsr, wrmsr, rdpmc, rdtsc) and the control and debug registers." Correct me if I'm mistaken, but isn't this already implemented in llvm mc? I haven't searched for every instruction part of these architectures but I was able find to some of the privileged instructions for x86's .td definitions; h...

...at #VC can be nested. Nesting happens for + * example when the #VC handler has to call printk in the case of and error or + * when emulating 'movs' instructions. + * + * NMIs are another special case which can cause nesting of #VC handlers. The + * do_nmi() code path can cause #VC, e.g. for RDPMC. An NMI can also hit in + * the time window when the #VC handler is raised but before it has shifted its + * IST entry. To make sure any #VC raised from the NMI code path uses a new + * stack, the NMI handler unconditionally shifts the #VC handlers IST entry. + * This can cause one IST stack for #V...

...acking.c | 2 +- tools/perf/tests/mmap-thread-lookup.c | 2 +- tools/perf/tests/parse-no-sample-id-all.c | 2 +- tools/perf/tests/perf-targz-src-pkg | 10 +++++--- tools/perf/tests/perf-time-to-tsc.c | 3 +-- tools/perf/tests/rdpmc.c | 2 +- tools/perf/tests/sample-parsing.c | 2 +- tools/perf/ui/browser.h | 4 +-- tools/perf/ui/progress.h | 2 +- tools/perf/util/annotate.h | 2 +- tools/perf/util/build...

...acking.c | 2 +- tools/perf/tests/mmap-thread-lookup.c | 2 +- tools/perf/tests/parse-no-sample-id-all.c | 2 +- tools/perf/tests/perf-targz-src-pkg | 10 +++++--- tools/perf/tests/perf-time-to-tsc.c | 3 +-- tools/perf/tests/rdpmc.c | 2 +- tools/perf/tests/sample-parsing.c | 2 +- tools/perf/ui/browser.h | 4 +-- tools/perf/ui/progress.h | 2 +- tools/perf/util/annotate.h | 2 +- tools/perf/util/build...

Parallels proprietary hypervisor uses RDPMC as the hypercall instruction. As this instruction is supported since early P6 family, the drivers didn't even bother to check for the presence of the corresponding feature in CPUID. In QEMU/KVM, however, this instruction triggers #GP unless the VM is run with PMU (performance monitoring unit)...

...if (rel->type == VMI_RELOCATION_CALL_REL) { \ + paravirt_ops.opname = wrapper; \ + vmi_ops.cache = (void *)rel->eip; \ } \ } while (0) + /* * Activate the VMI interface and switch into paravirtualized mode @@ -731,13 +753,8 @@ static inline int __init activate_vmi(vo * rdpmc is not yet used in Linux */ - /* CPUID is special, so very special */ - reloc = call_vrom_long_func(vmi_rom, get_reloc, VMI_CALL_CPUID); - if (rel->type != VMI_RELOCATION_NONE) { - BUG_ON(rel->type != VMI_RELOCATION_CALL_REL); - vmi_ops.cpuid = (void *)rel->eip; - paravirt_ops.cpui...

...if (rel->type == VMI_RELOCATION_CALL_REL) { \ + paravirt_ops.opname = wrapper; \ + vmi_ops.cache = (void *)rel->eip; \ } \ } while (0) + /* * Activate the VMI interface and switch into paravirtualized mode @@ -731,13 +753,8 @@ static inline int __init activate_vmi(vo * rdpmc is not yet used in Linux */ - /* CPUID is special, so very special */ - reloc = call_vrom_long_func(vmi_rom, get_reloc, VMI_CALL_CPUID); - if (rel->type != VMI_RELOCATION_NONE) { - BUG_ON(rel->type != VMI_RELOCATION_CALL_REL); - vmi_ops.cpuid = (void *)rel->eip; - paravirt_ops.cpui...

On Thu, Apr 10, 2014 at 07:38:05PM +0200, Borislav Petkov wrote: > Rebased onto current acme/perf/core: > > -- > From: Borislav Petkov <bp at suse.de> > Date: Sun, 23 Feb 2014 12:04:53 +0100 > Subject: [PATCH] tools: Unify export.h > > So tools/ has been growing three, at a different stage of their > development export.h headers and so we should unite into one.

On Thu, Apr 10, 2014 at 07:38:05PM +0200, Borislav Petkov wrote: > Rebased onto current acme/perf/core: > > -- > From: Borislav Petkov <bp at suse.de> > Date: Sun, 23 Feb 2014 12:04:53 +0100 > Subject: [PATCH] tools: Unify export.h > > So tools/ has been growing three, at a different stage of their > development export.h headers and so we should unite into one.

...t, and I eventually want to get rid of it for #DB as well. The #VC handler needs to be able to nest, there is no way around that for various reasons, the two most important ones are: 1. The #VC -> NMI -> #VC case. #VCs can happen in the NMI handler, for example (but not exclusivly) for RDPMC. 2. In case of an error the #VC handler needs to print out error information by calling one of the printk wrappers. Those will end up doing IO to some console/serial port/whatever which will also cause #VC exceptions to emulate the access to the output devices. Using shift_ist is...

...h @@ -1,5 +1,9 @@ #ifndef __ASM_MSR_H #define __ASM_MSR_H + +#ifdef CONFIG_PARAVIRT +#include <asm/paravirt.h> +#else /* * Access to machine-specific registers (available on 586 and better only) @@ -77,6 +81,7 @@ static inline void wrmsrl (unsigned long __asm__ __volatile__("rdpmc" \ : "=a" (low), "=d" (high) \ : "c" (counter)) +#endif /* !CONFIG_PARAVIRT */ /* symbolic names for some interesting MSRs */ /* Intel defined MSRs. */ =================================================================== --- a/include/asm-i386/proce...