search for: rdest

...lt;32> OpcVal, dag ops, string asmstr, list<dag> pattern, InstrItinClass itin> : MyInst<ops, asmstr, pattern, itin> { let Inst{31-28} = OpcVal{31-28}; bits<6> Rsrc1; <===== Because destination is required first in operand ordering, bits<6> Rdest; <===== this ordering of declarations produces an incorrect GenCodeEmitter bits<16> Imm16; let Inst{27-22} = Rsrc1; let Inst{21-16} = Rdest; let Inst{15-0} = Imm16; } def ORI : MyFormat<0, (ops GPRegs:$Rdest, GPRegs:$Rsrc1, i32imm: $Imm16), ... In the generated emitter...

...am status register). ARM::SELECT would expand to a conditional move (moveq for example). Something similar is done by the Alpha backend: --------------------------------------------------------------------------------------------- def CMOVEQ : OForm4< 0x11, 0x24, "cmoveq $RCOND,$RTRUE,$RDEST", [(set GPRC:$RDEST, (select (seteq GPRC:$RCOND, 0), GPRC:$RTRUE, GPRC:$RFALSE))], s_cmov>; ---------------------------------------------------------------------------------------------- One thing that I don't understand is how the $RFALSE value is used. $RDEST must equ...

...te and none of the solutions seems to work for me. I have tried all combinations of using the trailing slash but it seems to have no effect. Does anyone know if -delete can work with -files-from? Here's the code: DIR="/mnt/backup/machine/oracle" FILES=".test_files.files" RDEST="10.0.150.52::machine-backup" find $DIR/lvl1 -maxdepth 1 -type f -mmin +30| /usr/bin/awk -F/ '{print $8"/"$9}' > /tmp/$FILES; rsync -ptrgoz --stats --delete --files-from=/tmp/$FILES $DIR/ $RDEST/ As I mentioned above I have tried all combinations of $DIR/ $DIR $RDEST...

I'm working on enhancing TableGen's type checking and it triggered with a problem in CellSPU's specification: XSHWv4i32: (set VECREG:v8i16:$rDest, (sext:v8i16 VECREG:v4i32:$rSrc)) It's complaining that v4i32 is not smaller than v8i16, which is true in the sense of vector bit size, and true in the sense of vector element size. To me, a sign extension from i32 to i16 makes no sense. >From the .td file, it looks as if src and dest typ...

...can destructively read at the end of a sequence of multiply-adds. The following sequence is required to so a simple multiply: acc r0 # clear accumulator, discarding its value (r0 reads as 0, and sinks writes) mac rSRC1, rSRC2 # multiply sources, store result in accumulator acc rDEST # fetch accumulator value to rDEST What's the best way to model simple MUL as this 3-insn sequence in the LLVM backend? Should the internal accumulation register be explicitly modeled as its own register class with a pattern to copy its value to a general register? Is it possible to code...

...w/o tblgen bitching up a storm about the "$" or the extra "bi" operands? - Immediates in a pattern: To move one register to another involves using the 3-operand OR instruction, but how do I encode an immediate w/o a type inference contradiction? def : Pat<(set R32C:$rDest, R32C:$rSrc), (ORIr32 R32C:$rSrc, 0)>; Thanks for the clue!

...ncat("bi ", !strconcat("$", "lr")). > > - Immediates in a pattern: To move one register to another involves > using the 3-operand OR instruction, but how do I encode an immediate > w/o a type inference contradiction? > > def : Pat<(set R32C:$rDest, R32C:$rSrc), > (ORIr32 R32C:$rSrc, 0)>; I am not sure what you mean. By 3-operand, you mean 2 source operand and 1 destination. I don't think the error you are seeing have anything to do with the immediate. For a def : Pat pattern, you don't need to specify the &qu...

Hello, I have been studying LLVM and started to create a new backend for a new RISC architecture. Now I need some help to get forward with my project. I'm quite new to compiling techniques so I'm sorry for the stupid questions. Question 1: My idea is to lower the select SDNode as follows: %res1 = %falseVal %res2 = setc %trueVal, %condition Where setc is conditional mov. The

...at the end of a sequence of multiply-adds. The > following sequence is required to so a simple multiply: > > acc r0 # clear accumulator, discarding its value (r0 reads as 0, > and sinks writes) > mac rSRC1, rSRC2 # multiply sources, store result in accumulator > acc rDEST # fetch accumulator value to rDEST > > What's the best way to model simple MUL as this 3-insn sequence in the > LLVM backend? > > Should the internal accumulation register be explicitly modeled as its > own register class with a pattern to copy its value to a general >...

On Apr 18, 2007, at 11:25 AM, Christopher Lamb wrote: > I noticed that the TableGen code emitter generator assumes that the > instruction fields are declared in the instruction format in the > same order that operands are defined. This seems like a bad > dependence to me, and that TableGen should match the name of field > declared in the instruction with the name of the

I noticed that the TableGen code emitter generator assumes that the instruction fields are declared in the instruction format in the same order that operands are defined. This seems like a bad dependence to me, and that TableGen should match the name of field declared in the instruction with the name of the operand in order to determine which operand of the MI to use . See

...s. The most important 16 bit instruction is data movement, this instruction can move register pairs in a single cycle, doing something like this: mov r25, r23 mov r24, r22 into: movw r25:r24, r23:r22 The key point here is that the movw instruction can only move data of fixed pairs in this way. movw Rdest+1:Rdest, Rorig+1:Rorig, so movw R25:R23, R21:R18 is illegal because registers pairs aren't adjacent. Explaining this as if it was for x86 may make things more clear. Suppose we only have 8bit regs (ah, al, cl, ch, bl, bh, etc...) with 8 bit instructions and a few 16 bit instrs that only work w...

...t;$", "lr")). Yep, $$ should work. >> - Immediates in a pattern: To move one register to another involves >> using the 3-operand OR instruction, but how do I encode an immediate >> w/o a type inference contradiction? >> >> def : Pat<(set R32C:$rDest, R32C:$rSrc), >> (ORIr32 R32C:$rSrc, 0)>; You current cannot specify move patterns in the .td file. You specify them with XXXRegisterInfo::copyRegToReg and XXXInstrInfo::isMoveInstr. See the PPC or Sparc backend for some simple examples. -Chris -- http://nondot.org/sabre...