Displaying 2 results from an estimated 2 matches for "rcinfo64".
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rcinfo
2016 Sep 24
2
RFC: Implement variable-sized register classes
...he "select" mechanism was intended to be extendable to be able to
select any object of any type based on the predefined mode. It is
entirely possible to use it in a similar way to what you describe below.
> def Is64Bit : Predicate<"Subtarget->is64Bit()">;
> def RCInfo64 : RCInfo<Is64Bit> {
> let RegTypes = [i64, v2i32, v4i16, v8i8];
> .....
> }
>
> class MyRegisterClass : RegisterClass<...> {
> let RCInfos = [RCInfo32, RCInfo64]
> }
With the RCInfo data, the new register class definition would be
something like
class MyReg...
2016 Sep 20
7
RFC: Implement variable-sized register classes
I have posted a patch that switches the API to one that supports this
(yet non-existent functionality) earlier:
https://reviews.llvm.org/D24631
The comments from that were incorporated into the following RFC.
Motivation:
Certain targets feature "variable-sized" registers, i.e. a situation
where the register size can be configured by a hardware switch. A
common instruction set