Displaying 12 results from an estimated 12 matches for "raword".
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2012 Nov 15
1
[LLVMdev] problem trying to write an LLVM register-allocation pass
...;m confused about the code that gets a preg for a given vreg.
Previously,you gave me code that takes into account the "allocation
order" and the "reserved regs", including the following:
BitVector reservedRegs = TRI->getReservedRegs(Fn);
ArrayRef<uint16_t> rawOrder = trc->getRawAllocationOrder(Fn);
ArrayRef<uint16_t>::iterator rItr = rawOrder.begin();
while (rItr != rawOrder.end()) {
while (rItr != rawOrder.end() && reservedRegs.test(*rItr)) {
++rItr;
}
As I recall, this prevented some...
2012 Nov 15
0
[LLVMdev] problem trying to write an LLVM register-allocation pass
Hi Susan,
Jakob just pointed me to 'MachineOperand::substPhysReg(unsigned preg, const
TargetRegisterInfo& TRI)'. That substitutes the given physreg for a virtreg
operand, taking the subregister index into account. That is what my
examples have been doing manually. Using substPhysReg would allow you to
tidy the Gcra code up slightly.
- Lang.
On Thu, Nov 15, 2012 at 11:21 AM, Lang
2012 Nov 15
2
[LLVMdev] problem trying to write an LLVM register-allocation pass
Thanks Jakob. I should have mentioned that earlier. :)
When you see mismatched sizes on operands it's a fair bet that the subreg
rewriting has gone wrong. I should have pulled that entirely out of the
preg search loop in the previous example.
Fixed version attached.
- Lang.
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2012 Nov 11
2
[LLVMdev] problem trying to write an LLVM register-allocation pass
...added
> headache filter out any reserved registers). I've attached a test-case
> where I do this somewhat manually. In short:
>
> int regClass = MRI->getRegClass(vreg)->getID();
> const TargetRegisterClass *trc = TRI->getRegClass(regClass);
> ArrayRef<uint16_t> rawOrder = trc->getRawAllocationOrder(Fn);
> ArrayRef<uint16_t>::iterator rItr = rawOrder.begin();
> while (reservedRegs.test(*rItr))
> ++rItr;
> preg = *rItr;
>
> Alternatively, you could use the AllocationOrder class
> (lib/CodeGen/AllocationOrder.h). This has the benefi...
2012 Nov 08
2
[LLVMdev] problem trying to write an LLVM register-allocation pass
..." for a class (and as an added
headache filter out any reserved registers). I've attached a test-case
where I do this somewhat manually. In short:
int regClass = MRI->getRegClass(vreg)->getID();
const TargetRegisterClass *trc = TRI->getRegClass(regClass);
ArrayRef<uint16_t> rawOrder = trc->getRawAllocationOrder(Fn);
ArrayRef<uint16_t>::iterator rItr = rawOrder.begin();
while (reservedRegs.test(*rItr))
++rItr;
preg = *rItr;
Alternatively, you could use the AllocationOrder class
(lib/CodeGen/AllocationOrder.h). This has the benefit of considering
register hints for...
2012 Nov 11
0
[LLVMdev] problem trying to write an LLVM register-allocation pass
...reserved registers). I've attached a test-case where I do this
>> somewhat manually. In short:
>>
>> int regClass = MRI->getRegClass(vreg)->getID();
>> const TargetRegisterClass *trc = TRI->getRegClass(regClass);
>> ArrayRef<uint16_t> rawOrder = trc->getRawAllocationOrder(Fn);
>> ArrayRef<uint16_t>::iterator rItr = rawOrder.begin();
>> while (reservedRegs.test(*rItr))
>> ++rItr;
>> preg = *rItr;
>>
>> Alternatively, you could use the AllocationOrder class
>> (...
2012 Nov 13
5
[LLVMdev] problem trying to write an LLVM register-allocation pass
...filter out any reserved registers). I've attached a test-case
>> where I do this somewhat manually. In short:
>>
>> int regClass = MRI->getRegClass(vreg)->getID();
>> const TargetRegisterClass *trc = TRI->getRegClass(regClass);
>> ArrayRef<uint16_t> rawOrder = trc->getRawAllocationOrder(Fn);
>> ArrayRef<uint16_t>::iterator rItr = rawOrder.begin();
>> while (reservedRegs.test(*rItr))
>> ++rItr;
>> preg = *rItr;
>>
>> Alternatively, you could use the AllocationOrder class
>> (lib/CodeGen/AllocationO...
2012 Nov 09
0
[LLVMdev] problem trying to write an LLVM register-allocation pass
...> added headache filter out any reserved registers). I've attached a
> test-case where I do this somewhat manually. In short:
>
> int regClass = MRI->getRegClass(vreg)->getID();
> const TargetRegisterClass *trc = TRI->getRegClass(regClass);
> ArrayRef<uint16_t> rawOrder = trc->getRawAllocationOrder(Fn);
> ArrayRef<uint16_t>::iterator rItr = rawOrder.begin();
> while (reservedRegs.test(*rItr))
> ++rItr;
> preg = *rItr;
>
> Alternatively, you could use the AllocationOrder class
> (lib/CodeGen/AllocationOrder.h). This has the benefi...
2012 Nov 13
0
[LLVMdev] problem trying to write an LLVM register-allocation pass
...t;> attached a test-case where I do this somewhat manually. In short:
>>>
>>> int regClass = MRI->getRegClass(vreg)->getID();
>>> const TargetRegisterClass *trc = TRI->getRegClass(regClass);
>>> ArrayRef<uint16_t> rawOrder = trc->getRawAllocationOrder(Fn);
>>> ArrayRef<uint16_t>::iterator rItr = rawOrder.begin();
>>> while (reservedRegs.test(*rItr))
>>> ++rItr;
>>> preg = *rItr;
>>>
>>> Alternatively, you could...
2012 Nov 14
1
[LLVMdev] problem trying to write an LLVM register-allocation pass
...where I do this somewhat manually. In
>>>> short:
>>>>
>>>> int regClass = MRI->getRegClass(vreg)->getID(**);
>>>> const TargetRegisterClass *trc = TRI->getRegClass(regClass);
>>>> ArrayRef<uint16_t> rawOrder = trc->getRawAllocationOrder(Fn)**;
>>>> ArrayRef<uint16_t>::iterator rItr = rawOrder.begin();
>>>> while (reservedRegs.test(*rItr))
>>>> ++rItr;
>>>> preg = *rItr;
>>>>
>>>>...
2012 Nov 07
0
[LLVMdev] problem trying to write an LLVM register-allocation pass
Hi Susan,
Sorry for the delayed response. Thanks for the test cases - I'm looking in
to this now.
- Lang.
On Mon, Nov 5, 2012 at 2:58 PM, Susan Horwitz <horwitz at cs.wisc.edu> wrote:
> Hi Lang,
>
> I looked more into one of the problems I'm now having, and I've attached 3
> files:
>
> Gcra.cpp is like your version except that for two specific vregs it uses
2012 Nov 05
2
[LLVMdev] problem trying to write an LLVM register-allocation pass
Hi Lang,
I looked more into one of the problems I'm now having, and I've attached
3 files:
Gcra.cpp is like your version except that for two specific vregs it uses
hard-coded pregs instead of the first in the corresponding class.
bug1.c is an input that causes the failed assertion for me. If I use
the non-debug version of LLVM-3.1 I instead get assembler errors like this:
Error: