search for: raregs

Displaying 6 results from an estimated 6 matches for "raregs".

[LLVMdev] Types inference in tblgen: Multiple exceptions
2011 Dec 10
5
[LLVMdev] Types inference in tblgen: Multiple exceptions
...end for a processor that has complex type registers. >> It has two functional units to perform complex multiplications. >> From clang, I emulate a complex multiplication using vectors and, at >> the IR, I got this tblgen-friendly pattern (real component) : >> >> (set RARegs:$dst, (insertelt RARegs:$src, >> (i16 (trunc (add >> (ncmul >> (sext (i16 (extractelt RARegs:$a, imm))), >> (sext (i16 (extractelt RARegs:$b, imm))) >> ), >> (ncmul >> (s...
[LLVMdev] Types inference in tblgen: Multiple exceptions
2011 Dec 09
2
[LLVMdev] Types inference in tblgen: Multiple exceptions
Hi all, I am writing a back-end for a processor that has complex type registers. It has two functional units to perform complex multiplications. From clang, I emulate a complex multiplication using vectors and, at the IR, I got this tblgen-friendly pattern (real component) : (set RARegs:$dst, (insertelt RARegs:$src, (i16 (trunc (add (ncmul (sext (i16 (extractelt RARegs:$a, imm))), (sext (i16 (extractelt RARegs:$b, imm))) ), (ncmul (sext (i16 (extractelt RARegs:$a, imm))), (sext (i16...
[LLVMdev] Types inference in tblgen: Multiple exceptions
2011 Dec 10
0
[LLVMdev] Types inference in tblgen: Multiple exceptions
...that has complex type registers. >>> It has two functional units to perform complex multiplications. >>>  From clang, I emulate a complex multiplication using vectors and, at >>> the IR, I got this tblgen-friendly pattern (real component) : >>> >>> (set RARegs:$dst, (insertelt RARegs:$src, >>>           (i16 (trunc (add >>>            (ncmul >>>             (sext (i16 (extractelt RARegs:$a, imm))), >>>             (sext (i16 (extractelt RARegs:$b, imm))) >>>             ), >>>            (ncmul >&g...
[LLVMdev] Types inference in tblgen: Multiple exceptions
2011 Dec 09
0
[LLVMdev] Types inference in tblgen: Multiple exceptions
...I am writing a back-end for a processor that has complex type registers. > It has two functional units to perform complex multiplications. >  From clang, I emulate a complex multiplication using vectors and, at > the IR, I got this tblgen-friendly pattern (real component) : > > (set RARegs:$dst, (insertelt RARegs:$src, >           (i16 (trunc (add >            (ncmul >             (sext (i16 (extractelt RARegs:$a, imm))), >             (sext (i16 (extractelt RARegs:$b, imm))) >             ), >            (ncmul >             (sext (i16 (extractelt RARegs:$a, imm...
[LLVMdev] Types inference in tblgen: Multiple exceptions
2011 Dec 10
1
[LLVMdev] Types inference in tblgen: Multiple exceptions
...e registers. >>>> It has two functional units to perform complex multiplications. >>>> From clang, I emulate a complex multiplication using vectors and, at >>>> the IR, I got this tblgen-friendly pattern (real component) : >>>> >>>> (set RARegs:$dst, (insertelt RARegs:$src, >>>> (i16 (trunc (add >>>> (ncmul >>>> (sext (i16 (extractelt RARegs:$a, imm))), >>>> (sext (i16 (extractelt RARegs:$b, imm))) >>>> ), >>>...
[LLVMdev] Types inference in tblgen: Multiple exceptions
2011 Dec 10
0
[LLVMdev] Types inference in tblgen: Multiple exceptions
...that has complex type registers. >>> It has two functional units to perform complex multiplications. >>> From clang, I emulate a complex multiplication using vectors and, at >>> the IR, I got this tblgen-friendly pattern (real component) : >>> >>> (set RARegs:$dst, (insertelt RARegs:$src, >>> (i16 (trunc (add >>> (ncmul >>> (sext (i16 (extractelt RARegs:$a, imm))), >>> (sext (i16 (extractelt RARegs:$b, imm))) >>> ), >>> (ncmul >&g...