Displaying 6 results from an estimated 6 matches for "ramfuc_unblock".
2017 Apr 10
0
[PATCH 10/11] nvkm/pmu/memx: init script -> memx translation
...6 offset, u8 ramcfg);
#endif
diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramfuc.h b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramfuc.h
index 9ef9d6a..614e716 100644
--- a/drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramfuc.h
+++ b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramfuc.h
@@ -160,6 +160,13 @@ ramfuc_unblock(struct ramfuc *ram)
nvkm_memx_unblock(ram->memx);
}
+static inline void
+ramfuc_init_run(struct ramfuc *ram, struct nvkm_bios *bios, u16 offset,
+ u8 ramcfg)
+{
+ nvkm_memx_init_run(ram->memx, bios, offset, ramcfg);
+}
+
#define ram_init(s,p) ramfuc_init(&(s)->base, (p))...
2014 Sep 29
0
[PATCH 2/7] fb/ramnva3: Link training for DDR3
...int
+ramfuc_train_result(struct nouveau_fb *pfb, u32 *result, u32 rsize)
+{
+ struct nouveau_pwr *ppwr = nouveau_pwr(pfb);
+
+ return nouveau_memx_train_result(ppwr, result, rsize);
+}
+
+static inline void
ramfuc_block(struct ramfuc *ram)
{
nouveau_memx_block(ram->memx);
@@ -162,6 +176,8 @@ ramfuc_unblock(struct ramfuc *ram)
#define ram_wait(s,r,m,d,n) ramfuc_wait(&(s)->base, (r), (m), (d), (n))
#define ram_nsec(s,n) ramfuc_nsec(&(s)->base, (n))
#define ram_wait_vblank(s) ramfuc_wait_vblank(&(s)->base)
+#define ram_train(s) ramfuc_train(&(s)->base)
+#...
2017 Apr 10
11
Preparations for Fermi DRAM clock changes
No, no, these will not implement Fermi reclocking. This set of patches
contains some of the preparatory work that I deem stable enough to
move upstream. Notable changes
- Training pattern upload routines from GK104+ now shared with GT215+
- Timing calculation for Fermi
- GDDR5 MR calculation from VBIOS timing table v1.0. Also useful for that
pesky GT 240.
- A routine to translate a VBIOS init
2017 Apr 10
14
RESEND Preparations for Fermi DRAM clock changes
Two patches went missing as a result of PEBCAK. No v2 marks as nothing
changed really. Just resending for easier enforcement of patch order
in other people's trees. Sorry for the noise.
Original message:
No, no, these will not implement Fermi reclocking. This set of patches
contains some of the preparatory work that I deem stable enough to
move upstream. Notable changes
- Training pattern
2014 Sep 29
18
Implement reclocking for DDR2, DDR3, GDDR3
Following a series of patches that implement memory reclocking for NVA3/5/8 with
DDR2, DDR3 and GDDR3 on board. I tested these patches on 6 different graphics
cards, but I expect reclocking now to work on many more.
Testers can pick up these patches and test it by enabling pstate
(nouveau.pstate=1). They should then be able to change clocks by writing to
/sys/class/drm/card0/device/pstate. Correct
2014 Sep 12
6
NVA3: Small misc mem reclocking fixes
Patch 1 fixes nva3 bailing due to not finding the right ramcfg
Patch 2 is a resend rebased on 3.17.0-rc4 for setting the vblank period
Patch 3-5 handle writes to per-partition registers, for which NVA3 does not
have special broadcast regs available.
Patch 6 removes local structs from NVA3 reclocking in favour of the already
existing "ram->base." variables, like in NVE0
As always,