search for: ramfuc_reg

...git a/drm/nouveau/nvkm/subdev/fb/ramgf100.c b/drm/nouveau/nvkm/subdev/fb/ramgf100.c index 4a9bd4f1..feb8820c 100644 --- a/drm/nouveau/nvkm/subdev/fb/ramgf100.c +++ b/drm/nouveau/nvkm/subdev/fb/ramgf100.c @@ -717,7 +717,7 @@ gf100_ram_new_(const struct nvkm_ram_func *func, ram->fuc.r_0x10f9b4 = ramfuc_reg(0x10f9b4); ram->fuc.r_0x10fb04 = ramfuc_reg(0x10fb04); ram->fuc.r_0x10fb08 = ramfuc_reg(0x10fb08); - ram->fuc.r_0x137310 = ramfuc_reg(0x137300); + ram->fuc.r_0x137300 = ramfuc_reg(0x137300); ram->fuc.r_0x137310 = ramfuc_reg(0x137310); ram->fuc.r_0x137360 = ramfuc_reg(0x137...

.../nouveau/nvkm/subdev/fb/ramgf100.c >> index 4a9bd4f1..feb8820c 100644 >> --- a/drm/nouveau/nvkm/subdev/fb/ramgf100.c >> +++ b/drm/nouveau/nvkm/subdev/fb/ramgf100.c >> @@ -717,7 +717,7 @@ gf100_ram_new_(const struct nvkm_ram_func *func, >> ram->fuc.r_0x10f9b4 = ramfuc_reg(0x10f9b4); >> ram->fuc.r_0x10fb04 = ramfuc_reg(0x10fb04); >> ram->fuc.r_0x10fb08 = ramfuc_reg(0x10fb08); >> - ram->fuc.r_0x137310 = ramfuc_reg(0x137300); >> + ram->fuc.r_0x137300 = ramfuc_reg(0x137300); >> ram->fuc.r_0x137310 =...

...t a/drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramgf100.c b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramgf100.c index fffd01a..6ebdc4c 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramgf100.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramgf100.c @@ -48,11 +48,7 @@ struct gf100_ramfuc { struct ramfuc_reg r_0x137390; - struct ramfuc_reg r_0x10f290; - struct ramfuc_reg r_0x10f294; - struct ramfuc_reg r_0x10f298; - struct ramfuc_reg r_0x10f29c; - struct ramfuc_reg r_0x10f2a0; + struct ramfuc_reg r_0x10f290[5]; struct ramfuc_reg r_0x10f300; struct ramfuc_reg r_0x10f338; @@ -104,6 +100,50 @@ str...

Following a series of patches that implement memory reclocking for NVA3/5/8 with DDR2, DDR3 and GDDR3 on board. I tested these patches on 6 different graphics cards, but I expect reclocking now to work on many more. Testers can pick up these patches and test it by enabling pstate (nouveau.pstate=1). They should then be able to change clocks by writing to /sys/class/drm/card0/device/pstate. Correct

...iming.h> #include <subdev/clock/nva3.h> #include <subdev/clock/pll.h> +#include <subdev/timer.h> + +#include <engine/fifo.h> + #include <core/option.h> #include "ramfuc.h" @@ -39,11 +45,14 @@ struct nva3_ramfuc { struct ramfuc base; + struct ramfuc_reg r_0x001610; + struct ramfuc_reg r_0x001700; struct ramfuc_reg r_0x004000; struct ramfuc_reg r_0x004004; struct ramfuc_reg r_0x004018; struct ramfuc_reg r_0x004128; struct ramfuc_reg r_0x004168; + struct ramfuc_reg r_0x100080; struct ramfuc_reg r_0x100200; struct ramfuc_reg r_0x100210;...

..., 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/nouveau/core/subdev/fb/ramfuc.h b/drivers/gpu/drm/nouveau/core/subdev/fb/ramfuc.h index 0f57fcf..04e3849 100644 --- a/drivers/gpu/drm/nouveau/core/subdev/fb/ramfuc.h +++ b/drivers/gpu/drm/nouveau/core/subdev/fb/ramfuc.h @@ -26,7 +26,7 @@ ramfuc_reg2(u32 addr1, u32 addr2) }; } -static inline struct ramfuc_reg +static noinline struct ramfuc_reg ramfuc_reg(u32 addr) { return ramfuc_reg2(addr, addr); -- 2.0.0.526.g5318336

...t a/drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramgf100.c b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramgf100.c index 6ebdc4c..b4fe3bb 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramgf100.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramgf100.c @@ -50,11 +50,7 @@ struct gf100_ramfuc { struct ramfuc_reg r_0x10f290[5]; - struct ramfuc_reg r_0x10f300; - struct ramfuc_reg r_0x10f338; - struct ramfuc_reg r_0x10f340; - struct ramfuc_reg r_0x10f344; - struct ramfuc_reg r_0x10f348; + struct ramfuc_reg r_mr[9]; struct ramfuc_reg r_0x10f910; struct ramfuc_reg r_0x10f914; @@ -226,6 +222,19 @@ gf100_...

Patch 1 fixes nva3 bailing due to not finding the right ramcfg Patch 2 is a resend rebased on 3.17.0-rc4 for setting the vblank period Patch 3-5 handle writes to per-partition registers, for which NVA3 does not have special broadcast regs available. Patch 6 removes local structs from NVA3 reclocking in favour of the already existing "ram->base." variables, like in NVE0 As always,

...bdev/fb/ramgf100.c b/drm/nouveau/nvkm/subdev/fb/ramgf100.c > index 4a9bd4f1..feb8820c 100644 > --- a/drm/nouveau/nvkm/subdev/fb/ramgf100.c > +++ b/drm/nouveau/nvkm/subdev/fb/ramgf100.c > @@ -717,7 +717,7 @@ gf100_ram_new_(const struct nvkm_ram_func *func, > ram->fuc.r_0x10f9b4 = ramfuc_reg(0x10f9b4); > ram->fuc.r_0x10fb04 = ramfuc_reg(0x10fb04); > ram->fuc.r_0x10fb08 = ramfuc_reg(0x10fb08); > - ram->fuc.r_0x137310 = ramfuc_reg(0x137300); > + ram->fuc.r_0x137300 = ramfuc_reg(0x137300); > ram->fuc.r_0x137310 = ramfuc_reg(0x137310); > ram->fuc...

No, no, these will not implement Fermi reclocking. This set of patches contains some of the preparatory work that I deem stable enough to move upstream. Notable changes - Training pattern upload routines from GK104+ now shared with GT215+ - Timing calculation for Fermi - GDDR5 MR calculation from VBIOS timing table v1.0. Also useful for that pesky GT 240. - A routine to translate a VBIOS init

Two patches went missing as a result of PEBCAK. No v2 marks as nothing changed really. Just resending for easier enforcement of patch order in other people's trees. Sorry for the noise. Original message: No, no, these will not implement Fermi reclocking. This set of patches contains some of the preparatory work that I deem stable enough to move upstream. Notable changes - Training pattern

In bulletpoints: - Add some support for G94 and G96 reclocking. Has been tested on literally two cards, which is hardly adequate as "full coverage". On the other hand, the changes were small enough to make me confident this might work for others as well. - Fix NV50 wait for VBLANK when no monitor is plugged in. - Voltage related inprovements for GT21x. - Slightly improve Keplers

Hello, Attached a small patch that correctly identifies the DLLoff bit for >=GF100. Marked RFC because I haven't seen any GDDR5 samples that *enable* the DLL. I'd like to verify whether the DLL should be reset when enabled. Could increase likelihood of succesfull reclock. Ben: could you do some experiments with this bit to see if GDDR5 needs some DLL reset logic? Thanks, and happy

...-git a/drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramgt215.c b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramgt215.c index 6abd0e3..fa85942 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramgt215.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramgt215.c @@ -75,7 +75,7 @@ struct gt215_ramfuc { struct ramfuc_reg r_gpio[4]; }; -struct gt215_ltrain { +struct gt215_ram_train_ddr3 { enum { NVA3_TRAIN_UNKNOWN, NVA3_TRAIN_UNSUPPORTED, @@ -92,11 +92,11 @@ struct gt215_ltrain { struct gt215_ram { struct nvkm_ram base; struct gt215_ramfuc fuc; - struct gt215_ltrain ltrain; + struct gt215_ram_train_d...