search for: ram_train

...block(ram->memx); @@ -162,6 +176,8 @@ ramfuc_unblock(struct ramfuc *ram) #define ram_wait(s,r,m,d,n) ramfuc_wait(&(s)->base, (r), (m), (d), (n)) #define ram_nsec(s,n) ramfuc_nsec(&(s)->base, (n)) #define ram_wait_vblank(s) ramfuc_wait_vblank(&(s)->base) +#define ram_train(s) ramfuc_train(&(s)->base) +#define ram_train_result(s,r,l) ramfuc_train_result((s), (r), (l)) #define ram_block(s) ramfuc_block(&(s)->base) #define ram_unblock(s) ramfuc_unblock(&(s)->base) diff --git a/drivers/gpu/drm/nouveau/core/subdev/fb/ramnva3....

Following a series of patches that implement memory reclocking for NVA3/5/8 with DDR2, DDR3 and GDDR3 on board. I tested these patches on 6 different graphics cards, but I expect reclocking now to work on many more. Testers can pick up these patches and test it by enabling pstate (nouveau.pstate=1). They should then be able to change clocks by writing to /sys/class/drm/card0/device/pstate. Correct

...0/fb/gddr5: note another semi-unknown 1e1d6b4 drm/nouveau/fb/gddr5: modify mr8 with high bits of CL/WR e7084c6 drm/nve0/fb/gddr5: fix calculation of RDQS setting 334565a drm/nve0/fb/gddr5: switch off some other random bit at some point 0189169 drm/nve0/fb/gddr5: punt all 10f910/914 accesses through ram_train d394fb1 drm/nve0/fb/gddr5: not all memory partitions are created equal dd95c8f drm/nve0/fb: typo in register name 0a0dc8f drm/nouveau/bios: make common code to handle ramcfg strap etc 5905439 drm/nve0/fb/gddr5: fix an assumption of sane memory controller layout 2daaf5b drm/nve0/fb/gddr5: fix behavi...