search for: ram_nsec

...DDR5: + ret = nvkm_gddr5_calc(&ram->base, false); + break; + default: + ret = -ENOSYS; + break; + } + /* determine current mclk configuration */ from = !!(ram_rd32(fuc, 0x1373f0) & 0x00000002); /*XXX: ok? */ @@ -354,9 +363,6 @@ gf100_ram_calc(struct nvkm_ram *base, u32 freq) ram_nsec(fuc, 2000); ram_wr32(fuc, 0x10f314, 0x00000001); ram_wr32(fuc, 0x10f210, 0x80000000); - ram_wr32(fuc, 0x10f338, 0x00300220); - ram_wr32(fuc, 0x10f300, 0x0000011d); - ram_nsec(fuc, 1000); } else { ram_wr32(fuc, 0x10f800, 0x00001800); ram_wr32(fuc, 0x13d8f4, 0x00000000); @@ -382,25 +...

...ruct nvkm_ram *base, u32 freq) } } + gf100_ram_timing_calc(ram, timing); + ret = ram_init(fuc, ram->base.fb); if (ret) return ret; @@ -314,28 +357,6 @@ gf100_ram_calc(struct nvkm_ram *base, u32 freq) ram_wr32(fuc, 0x10f338, 0x00300220); ram_wr32(fuc, 0x10f300, 0x0000011d); ram_nsec(fuc, 1000); - ram_wr32(fuc, 0x10f290, 0x02060505); - ram_wr32(fuc, 0x10f294, 0x34208288); - ram_wr32(fuc, 0x10f298, 0x44050411); - ram_wr32(fuc, 0x10f29c, 0x0000114c); - ram_wr32(fuc, 0x10f2a0, 0x42e10069); - ram_wr32(fuc, 0x10f614, 0x40044f77); - ram_wr32(fuc, 0x10f610, 0x40044f77); - ram_...

Following a series of patches that implement memory reclocking for NVA3/5/8 with DDR2, DDR3 and GDDR3 on board. I tested these patches on 6 different graphics cards, but I expect reclocking now to work on many more. Testers can pick up these patches and test it by enabling pstate (nouveau.pstate=1). They should then be able to change clocks by writing to /sys/class/drm/card0/device/pstate. Correct

From: Markus Elfring <elfring at users.sourceforge.net> Date: Wed, 21 Sep 2016 09:09:09 +0200 A few update suggestions were taken into account from static source code analysis. Markus Elfring (5): Use kmalloc_array() in nvbios_iccsense_parse() Use kmalloc_array() in gt215_link_train() Delete unnecessary braces Adjust a kzalloc() call in gt215_ram_new() Add space after an

...} - if (device->chipset == 0xa3 && freq > 500000) { + if (device->chipset == 0xa3 && freq > 500000) ram_mask(fuc, 0x100700, 0x00000006, 0x00000000); - } /* Final switch */ if (mclk.pll) { @@ -745,12 +743,11 @@ gt215_ram_calc(struct nvkm_ram *base, u32 freq) ram_nsec(fuc, 2000); /* Set RAM MR parameters and timings */ - for (i = 2; i >= 0; i--) { + for (i = 2; i >= 0; i--) if (ram_rd32(fuc, mr[i]) != ram->base.mr[i]) { ram_wr32(fuc, mr[i], ram->base.mr[i]); ram_nsec(fuc, 1000); } - } ram_wr32(fuc, 0x100220[3], timing[3]); ram...

In bulletpoints: - Add some support for G94 and G96 reclocking. Has been tested on literally two cards, which is hardly adequate as "full coverage". On the other hand, the changes were small enough to make me confident this might work for others as well. - Fix NV50 wait for VBLANK when no monitor is plugged in. - Voltage related inprovements for GT21x. - Slightly improve Keplers

Signed-off-by: Roy Spliet <rspliet at eclipso.eu> --- drivers/gpu/drm/nouveau/include/nvkm/subdev/bios/ramcfg.h | 1 + drivers/gpu/drm/nouveau/nvkm/subdev/bios/rammap.c | 3 ++- drivers/gpu/drm/nouveau/nvkm/subdev/bios/timing.c | 2 ++ drivers/gpu/drm/nouveau/nvkm/subdev/fb/gddr3.c | 6 ++++-- 4 files changed, 9 insertions(+), 3 deletions(-) diff --git

Hello, Attached a small patch that correctly identifies the DLLoff bit for >=GF100. Marked RFC because I haven't seen any GDDR5 samples that *enable* the DLL. I'd like to verify whether the DLL should be reset when enabled. Could increase likelihood of succesfull reclock. Ben: could you do some experiments with this bit to see if GDDR5 needs some DLL reset logic? Thanks, and happy

No, no, these will not implement Fermi reclocking. This set of patches contains some of the preparatory work that I deem stable enough to move upstream. Notable changes - Training pattern upload routines from GK104+ now shared with GT215+ - Timing calculation for Fermi - GDDR5 MR calculation from VBIOS timing table v1.0. Also useful for that pesky GT 240. - A routine to translate a VBIOS init

Two patches went missing as a result of PEBCAK. No v2 marks as nothing changed really. Just resending for easier enforcement of patch order in other people's trees. Sorry for the noise. Original message: No, no, these will not implement Fermi reclocking. This set of patches contains some of the preparatory work that I deem stable enough to move upstream. Notable changes - Training pattern

Adds reclocking for NVA0, and a whole lot of work for other cards. Had these patches collecting dust for a little, but tested them with both my NVA0, and Martin's a while back. Success not guaranteed, but should be quite a leap forward. Happy reviewing and testing. Cheers, Roy

...+ return nouveau_memx_train_result(ppwr, result, rsize); +} + +static inline void ramfuc_block(struct ramfuc *ram) { nouveau_memx_block(ram->memx); @@ -162,6 +176,8 @@ ramfuc_unblock(struct ramfuc *ram) #define ram_wait(s,r,m,d,n) ramfuc_wait(&(s)->base, (r), (m), (d), (n)) #define ram_nsec(s,n) ramfuc_nsec(&(s)->base, (n)) #define ram_wait_vblank(s) ramfuc_wait_vblank(&(s)->base) +#define ram_train(s) ramfuc_train(&(s)->base) +#define ram_train_result(s,r,l) ramfuc_train_result((s), (r), (l)) #define ram_block(s) ramfuc_block(&(s)-&...

...(s)->base, (p)) #define ram_exec(s,e) ramfuc_exec(&(s)->base, (e)) #define ram_have(s,r) ((s)->r_##r.addr[0] != 0x000000) @@ -121,5 +133,7 @@ ramfuc_wait_vblank(struct ramfuc *ram) #define ram_wait(s,r,m,d,n) ramfuc_wait(&(s)->base, (r), (m), (d), (n)) #define ram_nsec(s,n) ramfuc_nsec(&(s)->base, (n)) #define ram_wait_vblank(s) ramfuc_wait_vblank(&(s)->base) +#define ram_fb_disable(s) ramfuc_fb_disable(&(s)->base) +#define ram_fb_enable(s) ramfuc_fb_enable(&(s)->base) #endif diff --git a/drivers/gpu/drm/nouveau/cor...

Patch 1 and 2 implement wait-for-vblank, required to remove flicker when reclocking memory Patch 3 and 4 allow me to do things between waiting for VBLANK and disabling FB, like pause PFIFO and wait for the engines to idle. This minimises the time PFIFO is paused, thus maximises performance. The rest of the patches speak for themselves. As the actual memory reclocking script is still somewhat prone

Patch 1 fixes nva3 bailing due to not finding the right ramcfg Patch 2 is a resend rebased on 3.17.0-rc4 for setting the vblank period Patch 3-5 handle writes to per-partition registers, for which NVA3 does not have special broadcast regs available. Patch 6 removes local structs from NVA3 reclocking in favour of the already existing "ram->base." variables, like in NVE0 As always,

I've splitted my big series between the part which actually fixes the engine reclocking bits and the part handling voltage/clock updates on temperature change, so that the more reviewed parts can be merged in faster. This series fixes a lot of Engine reclocking issues found on Fermi, Kepler and all Maxwell generation GPUs. It does _not_ fix memory reclocking on Fermi. It mostly contains of