search for: ralinscan

...tity<unsigned int>, std::less<unsigned int>, std::allocator<unsigned int> >::erase (this=0xa6bd3f8, __first=..., __last=...) at /usr/local/gcc/4.5.2/lib/gcc/i686-pc-linux-gnu/4.5.2/../../../../include/c++/4.5.2/bits/stl_tree.h:1449 #14 0x00b52b58 in (anonymous namespace)::RALinScan::assignRegOrStackSlotAtInterval(llvm::LiveInterval*) () from /usr/local/llvm/svn-r128446/lib/libLLVM-3.0svn.so #15 0x0169dc00 in llvm::X86::GR32RegClass () from /usr/local/llvm/svn-r128446/lib/libLLVM-3.0svn.so Problem occurs when I am attempting to run a large module in JIT, from Execution...

Hi Yuri, > I am debugging the memory issue that manifests itself like this: > > *** glibc detected *** ../app/app.OWS: free(): invalid pointer: 0x0ad391fc *** try running under valgrind. Note that if the program being JIT'd corrupts memory then this can cause the JIT itself to blow up. Ciao, Duncan.

Hi, Is there a way for me to collect statistics about the number of loads/stores added by the "linearscan" register allocator (just like can be done with the "local" allocator)? I still haven't grokked very well the interaction between RALinScan and Spiller... Should I add those two statistics to the spiller's class? Thanks, -- Silvio Ricardo Cordeiro -------------- next part -------------- An HTML attachment was scrubbed... URL: <http://lists.llvm.org/pipermail/llvm-dev/attachments/20100815/66d2d2a7/attachment.html>

I'm running into a problem with subregs during trivial coalescing in the linear scan allocator. Should RALinScan::attemptTrivialCoalescing be allowed to coalesce a COPY that uses a subreg as a destination? I've got the following sequence of code (unfortunately for an out of tree target) that is moving 32 and 64 bit sub-registers around within a 128 bit register. By the time the register allocator runs th...

...deiro wrote: > > > Is there a way for me to collect statistics about the number of > loads/stores added by the "linearscan" register allocator (just like can be > done with the "local" allocator)? I still haven't grokked very well the > interaction between RALinScan and Spiller... Should I add those two > statistics to the spiller's class? > > RALinearScan asks the Spiller to spill a virtual register. The > StandardSpiller passes the request to LiveIntervals::addIntervalsForSpills. > Here, the spill and restore points are added to the VirtRe...

...remote "origin"] fetch = +refs/notes/commits:refs/notes/commits And "git fetch origin" You can see like below; commit a2010a39da6a56317fda432954aadafb8241e1a4 Author: NAKAMURA Takumi <geek4civic at gmail.com> Date: Sun Nov 13 10:33:10 2011 Prune more RALinScan. RALinScan was also here! Notes: git-svn-rev: 144487 * What would be made happier with it? - Fast pulling and checking-out - Work with traditional llvm.git, clang.git &c. llvm-project.git shares each root commit of subproject. - Ability to bisect inter projects (eg. tracking clang...

...io Ricardo Cordeiro wrote: > > > Is there a way for me to collect statistics about the number of loads/stores added by the "linearscan" register allocator (just like can be done with the "local" allocator)? I still haven't grokked very well the interaction between RALinScan and Spiller... Should I add those two statistics to the spiller's class? hmm, having information if an operation is (a, or part of a) spill generated by the register allocation would be benefical in some cases; Those memory operations cannon alias with any other memory operations in the code,...

...2 PM, Silvio Ricardo Cordeiro wrote: > Is there a way for me to collect statistics about the number of loads/stores added by the "linearscan" register allocator (just like can be done with the "local" allocator)? I still haven't grokked very well the interaction between RALinScan and Spiller... Should I add those two statistics to the spiller's class? RALinearScan asks the Spiller to spill a virtual register. The StandardSpiller passes the request to LiveIntervals::addIntervalsForSpills. Here, the spill and restore points are added to the VirtRegMap. No spill code has...

I'm sorry, I don't know what you were looking for. The first 5 were scattered amidst different e-mails. The others have to do with following what "RAFast" and "RALinScan" as examples. It's a linker error, and I do not know why only opt and bugpoint does not compiler, and why llc does not show my reg alloc pass anymore. It worked before the API change e-mail was released. 1) I created my .cpp file RegAllocJDKunk.cpp in llvm/lib/CodeGen/ directory. 2) I upd...

...in's. One question, just to be sure I understand you correctly. You mean that after the RegAlloc has assigned physical registers to LiveIntervals and before it calls the VRM to rewrite the function, it should explicitly add lives-ins for each MBB, just like LinearScan does it at the end of the RALinScan::linearScan() function??? E.g. like this: // Add live-ins to every BB except for entry. Also perform trivial coalescing. MachineFunction::iterator EntryMBB = mf_->begin(); SmallVector<MachineBasicBlock*, 8> LiveInMBBs; for (LiveIntervals::iterator i = li_->begin(), e = li_-&gt...

...Gen/RegisterCoalescer.h" #include "llvm/CodeGen/SSARegMap.h" #include "llvm/Target/MRegisterInfo.h" #include "llvm/Target/TargetMachine.h" @@ -47,7 +49,8 @@ static unsigned numIterations = 0; static unsigned numIntervals = 0; - struct VISIBILITY_HIDDEN RALinScan : public MachineFunctionPass { + struct VISIBILITY_HIDDEN RALinScan : public MachineFunctionPass, + public RegisterAllocator { static char ID; RALinScan() : MachineFunctionPass((intptr_t)&ID) {} @@ -96,7 +99,10 @@ virtual void getAnalysi...

On Jul 11, 2007, at 11:39 AM, David Greene wrote: > On Wednesday 11 July 2007 12:41, Tanya M. Lattner wrote: > >> I think the coalescer should be flexible enough to be run >> independent of >> the register allocator. For example, you may want to expose the >> copies >> induced by transforming out of SSA to the scheduler. If the >> scheduler is

...it move patterns, and at least it compiles correctly now: i1_ls: R0.H = HI(i1_l); R0.L = LO(i1_l); P0 = R0; R0.H = HI(i1_s); R0.L = LO(i1_s); R1 = B[P0] (Z); R2 = 1 (X); P0 = R0; R0 = R1 & R2; B[P0] = R0; RTS; The moves (P0 = R0) did not get optimized away by the register allocator. RALinScan::attemptTrivialCoalescing almost succeeded; it got as far as testing if the source register R0 is contained in the destination regclass (P). It isn't, so the move stayed in. The problem is that the source register is allocated before coalescing is attempted. The destination regclass does not...

Jeff Kunkel <jdkunk3 at gmail.com> writes: > I ran cmake to build the visual studio projects. Then I included my > code under the Visual Studio interface, but I placed my code separate > from the CodeGen code. Visual studio was smart enough to compile and > link in my code into the CodeGen library. Thus, I did not need to add > my code into the same directory as the CodeGen

On Jan 13, 2009, at 12:27 AM, Roman Levenstein <romix.llvm at googlemail.com > wrote: > 2009/1/13 Evan Cheng <echeng at apple.com>: >> >> On Jan 7, 2009, at 2:48 AM, Roman Levenstein wrote: >> >>> bb368: 0x8fdad00, LLVM BB @0x8fc2c98, ID#1: >>> Predecessors according to CFG: 0x8fdac90 (#0) >>> %R0<def> = MOVi 0, 14, %reg0,

2009/1/13 Evan Cheng <echeng at apple.com>: > > On Jan 7, 2009, at 2:48 AM, Roman Levenstein wrote: > >> bb368: 0x8fdad00, LLVM BB @0x8fc2c98, ID#1: >> Predecessors according to CFG: 0x8fdac90 (#0) >> %R0<def> = MOVi 0, 14, %reg0, %reg0 >> *** STR %LR<kill>, %R0<kill>, %reg0, 0, 14, %reg0, Mem:ST(4,4) >> [0x8fc2d68 + 0]

...i1_ls: > R0.H = HI(i1_l); R0.L = LO(i1_l); > P0 = R0; > R0.H = HI(i1_s); R0.L = LO(i1_s); > R1 = B[P0] (Z); > R2 = 1 (X); > P0 = R0; > R0 = R1 & R2; > B[P0] = R0; > RTS; > > The moves (P0 = R0) did not get optimized away by the register > allocator. RALinScan::attemptTrivialCoalescing almost succeeded; it > got > as far as testing if the source register R0 is contained in the > destination regclass (P). It isn't, so the move stayed in. > > The problem is that the source register is allocated before coalescing > is attempted. Th...

I ran cmake to build the visual studio projects. Then I included my code under the Visual Studio interface, but I placed my code separate from the CodeGen code. Visual studio was smart enough to compile and link in my code into the CodeGen library. Thus, I did not need to add my code into the same directory as the CodeGen files, and I did not need to change the CMakeList.txt. The offical name is

On Mar 15, 2009, at 2:02 PM, Jakob Stoklund Olesen wrote: > Hi, > > I am writing a backend for the Blackfin processor from Analog > Devices. I > just started so I still have a lot to learn about the code > generator. So > far, I can compile test/CodeGen/Generic/BasicInstrs.ll correctly, but > that is about it. > > The Blackfin 32-bit registers divide naturally

Hi, I am writing a backend for the Blackfin processor from Analog Devices. I just started so I still have a lot to learn about the code generator. So far, I can compile test/CodeGen/Generic/BasicInstrs.ll correctly, but that is about it. The Blackfin 32-bit registers divide naturally into several classes. I have modelled these register classes without knowing anything about what the code