search for: raghavan

Displaying 20 results from an estimated 70 matches for "raghavan".

2017 Jul 31
1
LLVM's loop strength reduction module
...en execute the SolveRecurse() function? This would avoid some compile time overhead, wouldn’t? SolveRecurse() does not need to be called if an LSR use has an empty formulae set associated with it because even if you called it you would not get a solution from it, right? Thanks. Regards, Venugopal Raghavan From: qcolombet at apple.com [mailto:qcolombet at apple.com] Sent: Friday, July 07, 2017 2:16 AM To: Raghavan, Venugopal <Venugopal.Raghavan at amd.com> Cc: llvm-dev at lists.llvm.org; Madhur Amilkanthwar <madhur13490 at gmail.com> Subject: Re: [llvm-dev] LLVM's loop strength reduc...
2017 Sep 04
7
Reaching definitions on Machine IR post register allocation
Hi, Just to clarify I am looking for a whole machine function analysis not just something restricted to within a machine basic block. Thanks. Regards, Venu. From: Raghavan, Venugopal Sent: Saturday, September 02, 2017 12:56 PM To: llvm-dev at lists.llvm.org Subject: Reaching definitions on Machine IR post register allocation Hi, Given a definition of a register by a machine instruction in the Machine IR post register allocation, I would like to compute the set of u...
2017 Jul 06
3
LLVM's loop strength reduction module
Hi Raghavan, I concur no specific docs. What do you want to know specifically? Cheers, -Quentin > On Jul 5, 2017, at 11:16 PM, Madhur Amilkanthwar via llvm-dev <llvm-dev at lists.llvm.org> wrote: > > AFAIK, no official doc. > You can probably get better help if you ask specific questions (...
2017 Nov 24
2
Reaching definitions on Machine IR post register allocation
...my test cases possibly due to the fact that my change is incorrect or incomplete. Apart from adding extra register units, do you need to do anything else? If you have the changes you made, I would be grateful if you can share it. Thanks. Regards, Venu. On Tue, Nov 14, 2017 at 8:54 AM, Venugopal Raghavan <venur2005 at gmail.com> wrote: > Hi Krzysztof, > > Thanks for the reply. > > Since a data flow edge is missing, I thought that it could be a > correctness issue and not just a precision issue. But, on second thoughts, > maybe it isn't because the edge from the impli...
2017 Sep 12
6
Reaching definitions on Machine IR post register allocation
Hi Venu, > On Sep 11, 2017, at 11:00 PM, Raghavan, Venugopal via llvm-dev <llvm-dev at lists.llvm.org> wrote: > > Hi Krzysztof, > > Thanks for your reply. > > I agree that adding extra register units for x86 would be the right way to fix this. Do you know if there is a plan to fix this? No concrete plan, no. We've b...
2017 Nov 01
2
Reaching definitions on Machine IR post register allocation
...from doing further work on this because of the X86 partial definition issue mentioned above to which Krzysztof drew my attention. Regards, Venu. -----Original Message----- From: Geoff Berry [mailto:gberry at codeaurora.org] Sent: Tuesday, October 31, 2017 8:33 PM To: llvm-dev at lists.llvm.org; Raghavan, Venugopal <Venugopal.Raghavan at amd.com> Subject: Re: [llvm-dev] Reaching definitions on Machine IR post register allocation Hi Venu, FWIW, I have a pass that does copy propagation after RA [1] (currently only within a basic block) that should be enabled some time in the not-too-distant f...
2017 Oct 31
2
Reaching definitions on Machine IR post register allocation
...isters are still present, which is what my current patch does, and is the source of complexity that I'm trying to eliminate). [1] https://reviews.llvm.org/D30751 [2] https://reviews.llvm.org/D39400 D39400 WIP: [MachineOperand][MIR] Add isRenamable to MachineOperand. On 10/31/2017 5:49 AM, Raghavan, Venugopal via llvm-dev wrote: > Hi Krzysztof, > > Thanks a lot for taking the time to write a detailed explanation. I > think I understand things better now. > > I am trying to see if I can use RDF for X86 assuming I can add more > register units for X86 so that the partia...
2017 Nov 13
2
Reaching definitions on Machine IR post register allocation
...ny special treatment of these to avoid the dependency issues, but the presence of these will reduce the precision of RDF. You can try to revert r300369 and see if it helps. It won't hurt Hexagon, so if helps X86, we could consider bringing that code back. -Krzysztof On 11/10/2017 6:52 AM, Raghavan, Venugopal via llvm-dev wrote: > Hi, > > For a test case that I ran I am seeing something in the RDF graph that I > do not quite understand. I think there is an data flow edge that is > missing but most likely I am wrong. > > The relevant portion of IR looks like this: >...
2017 Jul 06
2
LLVM's loop strength reduction module
Hi, My name is Venugopal Raghavan and I work in AMD. I was trying to understand the code in the file LoopStrengthReduce.cpp but I am making very slow progress. Is there any additional documentation available that would help me understand the code, like a PPT presentation or a design document or maybe a paper? I did not find anythi...
2011 Jun 21
3
Acoustic echo cancellation
On Tue, 2011-06-21 at 20:18 +0200, Kadinger Andr?s wrote: > 2011.06.21. 19:22 keltez?ssel, Arun Raghavan ?rta: > > Hi Andras, others, > > > > Andras Kadinger<bandit<at> surfnonstop.com> writes: > >> > >> Daniel, > >> I recommend you to start from a simple case and gradually progress > >> towards your goal. > >>...
2020 Apr 08
3
Error with perf2bolt in LLVM BOLT
...awning perf job to read process events PERF2BOLT: spawning perf job to read task events BOLT-INFO: Target architecture: x86_64 *BOLT-ERROR: input file was processed by BOLT. Cannot re-optimize.* Not sure why I get the above error. Can someone who has used BOLT help me? Thanks. Regards, Venugopal Raghavan. -------------- next part -------------- An HTML attachment was scrubbed... URL: <http://lists.llvm.org/pipermail/llvm-dev/attachments/20200408/248ba556/attachment.html>
2011 Jun 23
1
Acoustic echo cancellation
2011.06.21. 22:57 keltez?ssel, Arun Raghavan ?rta: > On Tue, 2011-06-21 at 11:39 -0700, Arun Raghavan wrote: > [...] >> I'm also running this on x86 (x86_64, technically), and it's all >> floating-point, so I guess this is a regression somewhere. Will try to >> see if I can run it without any optimisations if p...
2004 Aug 16
2
using nls to fit a four parameter logistic model
Shalini Raghavan 3M Pharmaceuticals Research Building 270-03-A-10, 3M Center St. Paul, MN 55144 E-mail: sraghavan at mmm.com Tel: 651-736-2575 Fax: 651-733-5096 ----- Forwarded by Shalini Raghavan/US-Corporate/3M/US on 08/16/2004 11:25 AM -----...
2011 Jun 22
2
Acoustic echo cancellation
On 06/22/2011 04:57 AM, Arun Raghavan wrote: > On Tue, 2011-06-21 at 11:39 -0700, Arun Raghavan wrote: > [...] >> I'm also running this on x86 (x86_64, technically), and it's all >> floating-point, so I guess this is a regression somewhere. Will try to >> see if I can run it without any optimisations if...
2011 May 24
3
AEC learning behaviour
Hello, We've integrated the speex echo canceller into PulseAudio, and coupled with the AGC/denoiser, it works reasonably well and has been a breeze to plug in, so thank you! One thing we're seeing, though, is that the canceller seems to take some time (a few seconds) to "learn", so initially the echo is clearly audible and it slowly fades out. This sometimes occurs in the middle
2008 Jul 29
2
Hi I am vinod, I want to set up simple Samba PDC using tdbsam password backend. samba is installed on fedora 8 GNU/Linux. my network is about 30 windowsXP Pro. SP-2 static IP addressed machines. total no users about : 40 my network is : 192.168.1. sa
...a server is *: 192.168.1.10* windowsXP Pro. SP-2 clients : *192.168.1.11* to *192.168.1.40 *I want the users to be able to access there files stored in the Samba server from any client. I have no DNS server. I have no DHCP server. can any one help me to setup SAMBA PDC . Thanks. Vinod Raghavan B.A.R.C. BOMBAY INDIA vinodrag@gmail.com
2001 Aug 27
5
Importing file from Excel
Hi, I have a basic import problem. I tried to import a comma delimited "boston.csv" from C drive and gave the following command at R prompt >read.csv(c:\boston.csv,sep=",",dec=".",fill=TRUE) Error: syntax error can any one help to debugg the code.I am using R version 1.3 for windows with regards srinivas __________________________________________________ Do
2010 Dec 08
3
Confidence Intervals for Odds Ratios in multivariate logistic regression
Hi all, I am trying to fit a logistic regression for a bivariate response using five independent variables in a stepwise procedure. My outputs look okay but does any one know (or is there any literature on) how the confidence intervals are calculated for the reported odds ratios..? Thanks! [[alternative HTML version deleted]]
2017 Dec 19
2
MemorySSA question
...With respect to that model, memorySSA is right. The value of A could depend > on the abstract heap state of the definition of array "e". > > I'm on my phone, so this may not make much sense, but I hope this helps, > Siddharth. > > On Tue 19 Dec, 2017, 15:13 Venugopal Raghavan via llvm-dev, < > llvm-dev at lists.llvm.org> wrote: > >> Hi, >> >> I am new to MemorySSA and wanted to understand its capabilities. Hence I >> wrote the following program (test.c): >> >> int N; >> >> void test(int *restrict a, int *restri...
2011 May 24
0
AEC learning behaviour
...ates that something went "wrong" in the audio capture/playback. For example, that could be an overrun/underrun in the soundcard buffer, or the user changing a volume control after the AEC, or moving the speakers, ... anything that changes the impulse response. Jean-Marc Arun Raghavan <arun.raghavan at collabora.co.uk> a ?crit?: > Hello, > We've integrated the speex echo canceller into PulseAudio, and coupled > with the AGC/denoiser, it works reasonably well and has been a breeze to > plug in, so thank you! > > One thing we're seeing, though, is...