search for: ra_64

...alysis passes valid. Consider for example the following machine basic block: BB#0: derived from LLVM BB %entry Live Ins: %A0_64 %A1_64 %V0_64<def> = AND64 %A0_64<kill>, %A1_64<kill> %V0<def> = KILL %V0, %V0_64<imp-use,kill> PseudoReturn64 %RA_64 In this case we would like to move the AND64 instruction after the KILL instruction (generated from an identity COPY). What is the right thing to do with the KILL instruction given the fact that the machine function pass calls TRI.invalidateLiveness()? Can we simply delete any KILL instruction we...

Hi Akira, > I am running into a problem when I turn on post-RA scheduler with mode > "ANTIDEP_CRITICAL" for mips. > I'd appreciate if someone could explain what is going wrong here. All these passes are pretty sensitive to correct register liveness information. As a first step I'd check whether machine verifier reports no errors here. -- With best regards, Anton

...ots, not because it has detected any true violations. $ llc macroblock.llvm.mips64el.ll -mcpu=mips64r2 -O3 -o macroblock.s -mattr=n64 -verify-machineinstrs # After PreEmit passes # Machine code for function start_macroblock: Post SSA BB#0: derived from LLVM BB %entry Live Ins: %A0_64 %T9_64 %RA_64 %S3_64 %S2_64 %S1_64 %S0_64 BEQ %A0<kill>, %ZERO, <BB#2> NOP Successors according to CFG: BB#2 BB#1 # End machine code for function start_macroblock. *** Bad machine code: MBB exits via unconditional fall-through but doesn't have exactly one CFG successor! *** - functi...

I am running into a problem when I turn on post-RA scheduler with mode "ANTIDEP_CRITICAL" for mips. I'd appreciate if someone could explain what is going wrong here. This is the basic block before post RA scheduling (at PostRASchedulerList.cpp:322): *(gdb) #3 0x0000000000ed3d26 in runOnMachineFunction (this=0x20aa470, Fn=...) at lib/CodeGen/PostRASchedulerList.cpp:322 322