search for: r_mips_lo16

Displaying 11 results from an estimated 11 matches for "r_mips_lo16".

2015 Nov 21
2
[lld] R_MIPS_HI16 / R_MIPS_LO16 calculation
On Sat, Nov 21, 2015 at 9:28 AM, Rui Ueyama <ruiu at google.com> wrote: > On Fri, Nov 20, 2015 at 10:13 PM, Simon Atanasyan <simon at atanasyan.com> > wrote: >> >> In case of MIPS O32 ABI we have to find a matching R_MIPS_LO16 >> relocation to calculate R_MIPS_HI16 one because R_MIPS_HI16 uses >> combined addend (AHI << 16) + (short)ALO where AHI is original >> R_MIPS_HI16 addend and ALO is addend of the matching R_MIPS_LO16 >> relocation [1]. There are two methods to do matching and R_MIPS_...
2015 Nov 21
2
[lld] R_MIPS_HI16 / R_MIPS_LO16 calculation
Hi, I am working on support R_MIPS_HI16 / R_MIPS_LO16 in the new LLD and have a couple of questions. == Q1 In case of MIPS O32 ABI we have to find a matching R_MIPS_LO16 relocation to calculate R_MIPS_HI16 one because R_MIPS_HI16 uses combined addend (AHI << 16) + (short)ALO where AHI is original R_MIPS_HI16 addend and ALO is addend of the matc...
2015 Nov 21
2
[lld] R_MIPS_HI16 / R_MIPS_LO16 calculation
...>> >> On Sat, Nov 21, 2015 at 9:28 AM, Rui Ueyama <ruiu at google.com> wrote: >> > On Fri, Nov 20, 2015 at 10:13 PM, Simon Atanasyan <simon at atanasyan.com> >> > wrote: >> >> >> >> In case of MIPS O32 ABI we have to find a matching R_MIPS_LO16 >> >> relocation to calculate R_MIPS_HI16 one because R_MIPS_HI16 uses >> >> combined addend (AHI << 16) + (short)ALO where AHI is original >> >> R_MIPS_HI16 addend and ALO is addend of the matching R_MIPS_LO16 >> >> relocation [1]. There are tw...
2015 Nov 22
2
[lld] R_MIPS_HI16 / R_MIPS_LO16 calculation
...o we > have to pair them up before applying relocations? The correct formula for the combined addend is (AHI << 16) + (short)ALO. So the combined addend depends on both AHI and ALO addends, therefore ALO affects result of R_MIPS_HI16 relocation. Current version of bfd GNU linker looks up R_MIPS_LO16 relocation each time it needs to calculate R_MIPS_HI16 relocation. It uses `mips_elf_add_lo16_rel_addend` function for that (https://goo.gl/P7nb76). -- Simon Atanasyan
2012 Mar 22
2
[LLVMdev] Sorting relocation entries
...mp -dr z29.gas.o 748: 8f830000 lw v1,0(gp) 748: R_MIPS_GOT16 .bss 74c: 8f820000 lw v0,0(gp) 74c: R_MIPS_GOT16 .bss 750: 8c630000 lw v1,0(v1) 750: R_MIPS_LO16 .bss 754: 244245d4 addiu v0,v0,17876 754: R_MIPS_LO16 .bss gas reorders these relocations with the function in the following link: http://repo.or.cz/w/binutils.git/blob/master:/gas/config/tc-mips.c#l15222 $ mips--linux-gnu-readelf -r z2...
2012 Mar 19
2
[LLVMdev] Sorting relocation entries
...best way to sort relocation entries before they are written out in ELFObjectWriter::WriteRelocationsFragment? According to the Mips ABI documents I have, there are certain restrictions on the order relocations appear in the table (e.g. R_MIPS_HI16 and R_MIPS_GOT16 must be followed immediately by a R_MIPS_LO16). When I enable post RA scheduling, some of the restrictions are violated in the generated object code, which results in incorrect relocation values generated by the linker. I am considering imitating what gas does in function mips_frob_file (line 15522 of tc-mips.c) to fix this problem: http://r...
2012 Mar 22
0
[LLVMdev] Sorting relocation entries
...  748:       8f830000        lw      v1,0(gp) >                        748: R_MIPS_GOT16       .bss >     74c:       8f820000        lw      v0,0(gp) >                        74c: R_MIPS_GOT16       .bss >     750:       8c630000        lw      v1,0(v1) >                        750: R_MIPS_LO16        .bss >     754:       244245d4        addiu   v0,v0,17876 >                        754: R_MIPS_LO16        .bss > > > gas reorders these relocations with the function in the following link: > > http://repo.or.cz/w/binutils.git/blob/master:/gas/config/tc-mips.c#l15222 &gt...
2012 Mar 21
0
[LLVMdev] Sorting relocation entries
...tries before they are > written out in ELFObjectWriter::WriteRelocationsFragment? > > According to the Mips ABI documents I have, there are certain > restrictions on the order relocations appear in the table (e.g. > R_MIPS_HI16 and R_MIPS_GOT16 must be followed immediately by a > R_MIPS_LO16). When I enable post RA scheduling, some of the > restrictions are violated in the generated object code, which results > in incorrect relocation values generated by the linker. > > I am considering imitating what gas does in function mips_frob_file > (line 15522 of tc-mips.c) to fi...
2012 Mar 22
2
[LLVMdev] Sorting relocation entries
...00 lw v1,0(gp) >> 748: R_MIPS_GOT16 .bss >> 74c: 8f820000 lw v0,0(gp) >> 74c: R_MIPS_GOT16 .bss >> 750: 8c630000 lw v1,0(v1) >> 750: R_MIPS_LO16 .bss >> 754: 244245d4 addiu v0,v0,17876 >> 754: R_MIPS_LO16 .bss >> >> >> gas reorders these relocations with the function in the following link: >> >> http://repo.or.cz/w/binutils.git/blob/master:/...
2012 Mar 23
0
[LLVMdev] Sorting relocation entries
...,0(gp) >>>                        748: R_MIPS_GOT16       .bss >>>     74c:       8f820000        lw      v0,0(gp) >>>                        74c: R_MIPS_GOT16       .bss >>>     750:       8c630000        lw      v1,0(v1) >>>                        750: R_MIPS_LO16        .bss >>>     754:       244245d4        addiu   v0,v0,17876 >>>                        754: R_MIPS_LO16        .bss >>> >>> >>> gas reorders these relocations with the function in the following link: >>> >>> http://repo.or.cz/w/b...
2012 Mar 23
1
[LLVMdev] Sorting relocation entries
...gt; 748: R_MIPS_GOT16 .bss >>>> 74c: 8f820000 lw v0,0(gp) >>>> 74c: R_MIPS_GOT16 .bss >>>> 750: 8c630000 lw v1,0(v1) >>>> 750: R_MIPS_LO16 .bss >>>> 754: 244245d4 addiu v0,v0,17876 >>>> 754: R_MIPS_LO16 .bss >>>> >>>> >>>> gas reorders these relocations with the function in the following link: >>>> >&gt...