Displaying 7 results from an estimated 7 matches for "r_100720".
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20100720
2014 Sep 29
0
[PATCH 2/7] fb/ramnva3: Link training for DDR3
...r_0x111104;
+ struct ramfuc_reg r_0x1111e0;
+ struct ramfuc_reg r_0x111400;
struct ramfuc_reg r_0x611200;
struct ramfuc_reg r_mr[4];
};
+struct nva3_ltrain {
+ enum {
+ NVA3_TRAIN_UNKNOWN,
+ NVA3_TRAIN_UNSUPPORTED,
+ NVA3_TRAIN_ONCE,
+ NVA3_TRAIN_EXEC,
+ NVA3_TRAIN_DONE
+ } state;
+ u32 r_100720;
+ u32 r_1111e0;
+ u32 r_111400;
+ struct nouveau_mem *mem;
+};
+
struct nva3_ram {
struct nouveau_ram base;
struct nva3_ramfuc fuc;
+ struct nva3_ltrain ltrain;
};
+void
+nva3_link_train_calc(u32 *vals, struct nva3_ltrain *train)
+{
+ int i, lo, hi;
+ u8 median[8], bins[4] = {0, 0, 0, 0},...
2017 Apr 10
0
[PATCH 08/11] nvkm/ramgt215: Add train ptrn upload for GDDR5
...nvkm_wr32(device, 0x100538, 0x10000000 | (mem->offset >> 16));
nvkm_wr32(device, 0x1005a8, 0x0000ffff);
@@ -388,17 +424,50 @@ gt215_link_train_init(struct gt215_ram *ram)
nvkm_wr32(device, 0x700100 + (i << 2), pattern[i]);
nvkm_wr32(device, 0x1700, r001700);
- train->r_100720 = nvkm_rd32(device, 0x100720);
- train->r_1111e0 = nvkm_rd32(device, 0x1111e0);
- train->r_111400 = nvkm_rd32(device, 0x111400);
+ train_ddr3->r_100720 = nvkm_rd32(device, 0x100720);
+ train_ddr3->r_1111e0 = nvkm_rd32(device, 0x1111e0);
+ train_ddr3->r_111400 = nvkm_rd32(device, 0x11...
2014 Sep 29
18
Implement reclocking for DDR2, DDR3, GDDR3
Following a series of patches that implement memory reclocking for NVA3/5/8 with
DDR2, DDR3 and GDDR3 on board. I tested these patches on 6 different graphics
cards, but I expect reclocking now to work on many more.
Testers can pick up these patches and test it by enabling pstate
(nouveau.pstate=1). They should then be able to change clocks by writing to
/sys/class/drm/card0/device/pstate. Correct
2016 Sep 21
8
[PATCH 0/5] GPU-DRM-nouveau: Fine-tuning for five function implementations
From: Markus Elfring <elfring at users.sourceforge.net>
Date: Wed, 21 Sep 2016 09:09:09 +0200
A few update suggestions were taken into account
from static source code analysis.
Markus Elfring (5):
Use kmalloc_array() in nvbios_iccsense_parse()
Use kmalloc_array() in gt215_link_train()
Delete unnecessary braces
Adjust a kzalloc() call in gt215_ram_new()
Add space after an
2016 Sep 21
0
[PATCH 3/5] GPU-DRM-nouveau: Delete unnecessary braces
...km/subdev/fb/ramgt215.c
@@ -127,12 +127,11 @@ gt215_link_train_calc(u32 *vals, struct gt215_ltrain *train)
}
/* Find the best value for 0x1111e0 */
- for (i = 0; i < 4; i++) {
+ for (i = 0; i < 4; i++)
if (bins[i] > qty) {
bin = i + 3;
qty = bins[i];
}
- }
train->r_100720 = 0;
for (i = 0; i < 8; i++) {
@@ -729,9 +728,8 @@ gt215_ram_calc(struct nvkm_ram *base, u32 freq)
ram_mask(fuc, 0x1007e0, 0x22222222, r100760);
}
- if (device->chipset == 0xa3 && freq > 500000) {
+ if (device->chipset == 0xa3 && freq > 500000)
ram_mask(fu...
2017 Apr 10
11
Preparations for Fermi DRAM clock changes
No, no, these will not implement Fermi reclocking. This set of patches
contains some of the preparatory work that I deem stable enough to
move upstream. Notable changes
- Training pattern upload routines from GK104+ now shared with GT215+
- Timing calculation for Fermi
- GDDR5 MR calculation from VBIOS timing table v1.0. Also useful for that
pesky GT 240.
- A routine to translate a VBIOS init
2017 Apr 10
14
RESEND Preparations for Fermi DRAM clock changes
Two patches went missing as a result of PEBCAK. No v2 marks as nothing
changed really. Just resending for easier enforcement of patch order
in other people's trees. Sorry for the noise.
Original message:
No, no, these will not implement Fermi reclocking. This set of patches
contains some of the preparatory work that I deem stable enough to
move upstream. Notable changes
- Training pattern