search for: r_0_r2048b_1

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2018 Apr 10
1
64 bit mask in x86vshuffle instruction
...urn DAG.getNode(X86ISD::SHUF128_P64, DL, VT, Ops[0], Ops[1], DAG.getConstant(PermMask, DL, MVT::i64)); } Please help...i m really sorry for asking but i m stuck here..The code runs w/o error at the o/p it gives following assembly; P_256B_VSHUF64x2_QWORD R_0_R2048b_0, R_0_R2048b_1, R_0_R2048b_1, 236 # encoding: [] P_256B_VADD_DWORD R_0_R2048b_1, R_0_R2048b_1, R_0_R2048b_0 # encoding: [0x61,0x02,0x46,0x00,0x00,0x20,0x00,0x04,0x00,0x00,0x00] P_256B_VSHUF64x2_QWORD R_0_R2048b_0, R_0_R2048b_1, R_0_R2048b_1, 244 # encoding: [] P_256B_VADD_DWORD R_0_R2048b_1,...
2017 Aug 26
2
Error in generating Object Code for implemented assembly vector instructions
i want to emit binary code for the following implemented vector assembly instructions. P_256B_LOAD_DWORD R_0_R2048b_0, pword ptr [rip + b] P_256B_LOAD_DWORD R_0_R2048b_1, pword ptr [rip + c] P_256B_VADD R_0_R2048b_0, R_0_R2048b_1, R_0_R2048b_0 P_256B_STORE_DWORD pword ptr [rip + a], R_0_R2048b_0 I added the following lines in X86MCInstLower.cpp; unsigned NewOpc; switch (OutMI.getOpcode()) { default: llvm_unreachable("Invalid opcode");...