search for: r8

...) \ +(pred) movl reg = XSI_IPSR; \ + ;; \ +(pred) ld8 reg = [reg] + +#define MOV_FROM_IIM(reg) \ + movl reg = XSI_IIM; \ + ;; \ + ld8 reg = [reg] + +#define MOV_FROM_IIP(reg) \ + movl reg = XSI_IIP; \ + ;; \ + ld8 reg = [reg] + +.macro __MOV_FROM_IVR reg, clob + .ifc "\reg", "r8" + XEN_HYPER_GET_IVR + .exitm + .endif + .ifc "\clob", "r8" + XEN_HYPER_GET_IVR + ;; + mov \reg = r8 + .exitm + .endif + + mov \clob = r8 + ;; + XEN_HYPER_GET_IVR + ;; + mov \reg = r8 + ;; + mov r8 = \clob +.endm +#define MOV_FROM_IVR(reg, clob) __MOV_FROM_IVR reg, cl...

...pmu/fuc/memx.fuc > index ec03f9a4..1663bf94 100644 > --- a/drm/nouveau/nvkm/subdev/pmu/fuc/memx.fuc > +++ b/drm/nouveau/nvkm/subdev/pmu/fuc/memx.fuc > @@ -82,15 +82,15 @@ memx_train_tail: > // $r0 - zero > memx_func_enter: > #if NVKM_PPWR_CHIPSET == GT215 > - movw $r8 0x1610 > + mov $r8 0x1610 > nv_rd32($r7, $r8) > imm32($r6, 0xfffffffc) > and $r7 $r6 > - movw $r6 0x2 > + mov $r6 0x2 > or $r7 $r6 > nv_wr32($r8, $r7) > #else > - movw $r6 0x001620 > + mov $r6 0x...

...ev/pmu/fuc/memx.fuc b/drm/nouveau/nvkm/subdev/pmu/fuc/memx.fuc index ec03f9a4..1663bf94 100644 --- a/drm/nouveau/nvkm/subdev/pmu/fuc/memx.fuc +++ b/drm/nouveau/nvkm/subdev/pmu/fuc/memx.fuc @@ -82,15 +82,15 @@ memx_train_tail: // $r0 - zero memx_func_enter: #if NVKM_PPWR_CHIPSET == GT215 - movw $r8 0x1610 + mov $r8 0x1610 nv_rd32($r7, $r8) imm32($r6, 0xfffffffc) and $r7 $r6 - movw $r6 0x2 + mov $r6 0x2 or $r7 $r6 nv_wr32($r8, $r7) #else - movw $r6 0x001620 + mov $r6 0x001620 imm32($r7, ~0x00000aa2); nv_rd32($r8, $r6) and $r8 $r7 @@ -101,7 +101,7 @@ memx_func_enter: and $r8...

...metadata > explicitly or ParseOptionalCommaAlign needs to know about general metadata. > > My inkling is to fix ParseOptionalCommaAlign. Sound reasonable? Well, that's a rat's nest. I backed up and thought maybe I have the metadata syntax wrong. So I tried a bunch of things: %r8 = load <2 x double>* %r6, align 16, metadata !"nontemporal" %r8 = load <2 x double>* %r6, align 16, metadata !nontemporal %r8 = load <2 x double>* %r6, align 16, !{ metadata !"nontemporal" } %r8 = load <2 x double>* %r6, align 16, !{ metadata !nontemporal...

...); + DEFINE(OFFSET_VCPU_R4, offsetof(struct vcpu_guest_context, r4)); + DEFINE(OFFSET_VCPU_R5, offsetof(struct vcpu_guest_context, r5)); + DEFINE(OFFSET_VCPU_R6, offsetof(struct vcpu_guest_context, r6)); + DEFINE(OFFSET_VCPU_R7, offsetof(struct vcpu_guest_context, r7)); + DEFINE(OFFSET_VCPU_R8, offsetof(struct vcpu_guest_context, r8)); + DEFINE(OFFSET_VCPU_R9, offsetof(struct vcpu_guest_context, r9)); + DEFINE(OFFSET_VCPU_R10, offsetof(struct vcpu_guest_context, r10)); + DEFINE(OFFSET_VCPU_R11, offsetof(struct vcpu_guest_context, r11)); + DEFINE(OFFSET_VCPU_R12, offsetof(struct...

On Fri, 7 Feb 2014, Timothy B. Terriberry wrote: > Martin Storsjo wrote: >> This is required in order to build using the built-in assembler >> in clang. > > These patches break the gcc build (with "Error: bad instruction"). Ah, right, sorry about that. > Documentation I've seen is contradictory on which order ({cond}{size} or > {size}{cond}) is correct.

On Thursday 11 February 2010 13:31:58 David Greene wrote: > > Putting a bit (or multiple bits) in MachineMemOperand for this > > would also make sense. > > Is there any chance a MachineMemOperand will be shared by multiple > instructions? So I tried to do this: %r8 = load <2 x double>* %r6, align 16, !"nontemporal" and the assembler doesn't like it. Do I need to use named metadata? That would be rather inconvenient. The problem is this code in llvm-as: int LLParser::ParseLoad(Instruction *&Inst, PerFunctionState &PFS,...

...rsh r4, [r1] ldrsh r0, [r1, #2] rsb r14,r14,#0 @ r14 = -y[i] mla r5, r4, r14,r6 @ mem[0] = mem[1] - den[0]*y[i] ldrsh r4, [r1, #4] mla r6, r0, r14,r7 @ mem[1] = mem[2] - den[1]*y[i] ldrsh r0, [r1, #6] mla r7, r4, r14,r8 @ mem[2] = mem[3] - den[2]*y[i] ldrsh r4, [r1, #8] mla r8, r0, r14,r9 @ mem[3] = mem[4] - den[3]*y[i] ldrsh r0, [r1, #10] mla r9, r4, r14,r10 @ mem[4] = mem[5] - den[4]*y[i] ldrsh r4, [r1, #12] mla r10, r0, r14,r11 @ mem[5]...

...SUBS r2, r2, #1 ; j-- ; Stall SMLABB r6, r12, r10, r6 ; sum[0] = MAC16_16(sum[0],x,y_0) - LDRGTH r14, [r4], #2 ; r14 = *x++ + LDRHGT r14, [r4], #2 ; r14 = *x++ SMLABT r7, r12, r10, r7 ; sum[1] = MAC16_16(sum[1],x,y_1) SMLABB r8, r12, r11, r8 ; sum[2] = MAC16_16(sum[2],x,y_2) SMLABT r9, r12, r11, r9 ; sum[3] = MAC16_16(sum[3],x,y_3) @@ -319,7 +319,7 @@ xcorr_kernel_edsp_process4_done SMLABB r7, r14, r11, r7 ; sum[1] = MAC16_16(sum[1],x,y_2) LDRH r10, [r5], #2 ; r10 = y_4 = *y++ SM...

...SUBS r2, r2, #1 ; j-- ; Stall SMLABB r6, r12, r10, r6 ; sum[0] = MAC16_16(sum[0],x,y_0) - LDRGTH r14, [r4], #2 ; r14 = *x++ + LDRHGT r14, [r4], #2 ; r14 = *x++ SMLABT r7, r12, r10, r7 ; sum[1] = MAC16_16(sum[1],x,y_1) SMLABB r8, r12, r11, r8 ; sum[2] = MAC16_16(sum[2],x,y_2) SMLABT r9, r12, r11, r9 ; sum[3] = MAC16_16(sum[3],x,y_3) @@ -319,7 +319,7 @@ xcorr_kernel_edsp_process4_done SMLABB r7, r14, r11, r7 ; sum[1] = MAC16_16(sum[1],x,y_2) LDRH r10, [r5], #2 ; r10 = y_4 = *y++ SM...

...romising code Requires = [{ {} }]; // this looks like a string let Requires = [{ {AArch64::FeatureETE} }]. // which is not promising So I think that this would look something like: int reg_index = -1; ... let reg_index = [{ return XX::R8; }]; // or let reg_index = [{ {XX::R8} }]; However, then I get errors of the form: error: Value 'reg_index' of type 'int' is incompatible with initializer '[{ {XX::R8} }]' of type 'code' error: Value 'reg_index' of type 'int...

...t; but your litmus test: > > > PPC WRCnf+addrs > > "" > > { > > 0:r2=x; 0:r3=y; > > 1:r2=x; 1:r3=y; > > 2:r2=x; 2:r3=y; > > c=a; d=b; x=c; y=d; > > } > > P0 | P1 | P2 ; > > stw r3,0(r2) | lwz r8,0(r2) | lwz r8,0(r3) ; > > | stw r2,0(r3) | lwz r9,0(r8) ; > > exists > > (1:r8=y /\ 2:r8=x /\ 2:r9=c) > > Seems to be missing the address dependency on P1. You are quite correct! How about the following? As before, both herd and ppcmem say that the cyc...

...t; but your litmus test: > > > PPC WRCnf+addrs > > "" > > { > > 0:r2=x; 0:r3=y; > > 1:r2=x; 1:r3=y; > > 2:r2=x; 2:r3=y; > > c=a; d=b; x=c; y=d; > > } > > P0 | P1 | P2 ; > > stw r3,0(r2) | lwz r8,0(r2) | lwz r8,0(r3) ; > > | stw r2,0(r3) | lwz r9,0(r8) ; > > exists > > (1:r8=y /\ 2:r8=x /\ 2:r9=c) > > Seems to be missing the address dependency on P1. You are quite correct! How about the following? As before, both herd and ppcmem say that the cyc...

This patch set is intended for the next merge window. They are just enhancements of the already merged patches or ia64 porting from x86 paravirt techniques and that their quality is enough for merge. This patch set is for binary patch optimization for paravirt_ops. The binary patch optimization is important on native case because the paravirt_ops overhead can be reduced by converting indirect

This patch set is intended for the next merge window. They are just enhancements of the already merged patches or ia64 porting from x86 paravirt techniques and that their quality is enough for merge. This patch set is for binary patch optimization for paravirt_ops. The binary patch optimization is important on native case because the paravirt_ops overhead can be reduced by converting indirect

This patch set is intended for the next merge window. They are just enhancements of the already merged patches or ia64 porting from x86 paravirt techniques and that their quality is enough for merge. This patch set is for binary patch optimization for paravirt_ops which depends on the patch series I sent out, ia64/pv_ops, xen: more paravirtualization. The binary patch optimization is important on

This patch set is intended for the next merge window. They are just enhancements of the already merged patches or ia64 porting from x86 paravirt techniques and that their quality is enough for merge. This patch set is for binary patch optimization for paravirt_ops which depends on the patch series I sent out, ia64/pv_ops, xen: more paravirtualization. The binary patch optimization is important on

This patch set is for the next merge window. They are just enhancements of the already merged patches or ia64 porting from x86 paravirt techniques and that their quality is enough for merge. This patch set is for binary patch optimization for paravirt_ops which depends on the patch series I sent out, ia64/pv_ops, xen: more paravirtualization. The binary patch optimization is important on native

This patch set is for the next merge window. They are just enhancements of the already merged patches or ia64 porting from x86 paravirt techniques and that their quality is enough for merge. This patch set is for binary patch optimization for paravirt_ops which depends on the patch series I sent out, ia64/pv_ops, xen: more paravirtualization. The binary patch optimization is important on native

This patch set is for binary patch optimization for paravirt_ops. The binary patch optimization is important on native case because the paravirt_ops overhead can be reduced by converting indirect call into in-place execution or direct call. The first patch imports helper functions which themselves doesn't interesting things. The second patch replaces the indirect function calls with a