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r78247
2013 Dec 20
1
[LLVMdev] extra one cycle of getOperandLatency
...of such definition is latency of "2". That's not what I want.
After some digging around, I found the expression, "DefCycle - UseCycle + 1",
was first appearing in r79425 committed by David Goodwin, and seems
OperandCycles
was initially designed for ARM cortex-a8 (see also r79247 and r79436).
Then I checked "Cortex-A8 Technical Reference Manual - Instruction
Cycle Timing".
There are tables for instructions, for example
Data-processing instructions
Source1 Source2 Result1
Rn:E2 Rm:E2 Rd:E2
That means Rn and Rm are read at the begin of E2...