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I'm targeting a machine that can only load and store aligned 64-bit words, but I'd like to be able to pack 8-, 16-, and 32-bit values into these words. Loads will require various shifts and masks; stores are more complicated. Does LLVM provide any support for such things? Is there an example target I can look at for ideas? Thanks, Preston -------------- next part -------------- An HTML

Hi all, All of the data types are 32 bits and the pointer is 32 bit. Therefore, I need word adressing instead of byte adressing to use 8 GB memory. I was told that R600 uses word adressing and I looked at its codes but I could not find where the backends handles word adressing. Do you have any ideas about it? Thanks in advance. -------------- next part -------------- An HTML attachment was

...FBL_INT", cttz_zero_undef, VecALU>; > > diff --git a/lib/Target/R600/R600ISelLowering.cpp b/lib/Target/R600/R600ISelLowering.cpp > index 9b2b689..a28b76a 100644 > --- a/lib/Target/R600/R600ISelLowering.cpp > +++ b/lib/Target/R600/R600ISelLowering.cpp > @@ -89,6 +89,15 @@ R600TargetLowering::R600TargetLowering(TargetMachine &TM) : > setOperationAction(ISD::SELECT, MVT::v2i32, Expand); > setOperationAction(ISD::SELECT, MVT::v4i32, Expand); > > + // ADD, SUB overflow. These need to be Custom because > + // SelectionDAGLegalize::LegalizeOp (LegalizeDAG.c...

...s(&Subtarget.getInstrItineraryData()), > + mDump(false) > + > +{ > + // TLInfo uses InstrInfo so it must be initialized after. > + if (Subtarget.device()->getGeneration() <= AMDILDeviceInfo::HD6XXX) { > + InstrInfo = new R600InstrInfo(*this); > + TLInfo = new R600TargetLowering(*this); > + } else { > + InstrInfo = new SIInstrInfo(*this); > + TLInfo = new SITargetLowering(*this); > + } > +} > + > +AMDGPUTargetMachine::~AMDGPUTargetMachine() > +{ > +} > + > +bool AMDGPUTargetMachine::addPassesToEmitFile(PassManagerBase &PM,...