Displaying 5 results from an estimated 5 matches for "r600isellowering".
2014 Jun 20
2
[LLVMdev] Word Addressing
Hi all,
All of the data types are 32 bits and the pointer is 32 bit. Therefore, I
need word adressing instead of byte adressing to use 8 GB memory.
I was told that R600 uses word adressing and I looked at its codes but I
could not find where the backends handles word adressing.
Do you have any ideas about it?
Thanks in advance.
-------------- next part --------------
An HTML attachment was
2014 Oct 03
2
[LLVMdev] Weird problems with cos (was Re: [PATCH v3 2/3] R600: Add carry and borrow instructions. Use them to implement UADDO/USUBO)
...Vesely <jan.vesely at rutgers.edu>
>
> ---
> lib/Target/R600/AMDGPUISelLowering.h | 2 +
> lib/Target/R600/AMDGPUInstrInfo.td | 6 ++
> lib/Target/R600/AMDGPUSubtarget.h | 8 ++
> lib/Target/R600/EvergreenInstructions.td | 3 +
> lib/Target/R600/R600ISelLowering.cpp | 39 +++++++-
> test/CodeGen/R600/add.ll | 154 +++++++++++++++++--------------
> test/CodeGen/R600/sub.ll | 18 ++--
> test/CodeGen/R600/uaddo.ll | 17 +++-
> test/CodeGen/R600/usubo.ll | 23 ++++-
> 9 files ch...
2013 Aug 05
1
[LLVMdev] Promote MVT::f32 load/store to MVT::i32 cause infinite loop in LegalizeDAG?
On Mon, Aug 05, 2013 at 02:09:58PM -0400, Francois Pichet wrote:
> On my target store/load of f32 or i32 are equivalents.
> Previously I had duplicate instructions def in .td to map f32 and i32 to
> the same opcode.
>
> I deleted all that and I instead tried a new approach (to simplify things) :
>
> setOperationAction(ISD::STORE, MVT::f32, Promote);
>
2013 Aug 05
0
[LLVMdev] Promote MVT::f32 load/store to MVT::i32 cause infinite loop in LegalizeDAG?
On Mon, Aug 5, 2013 at 2:25 PM, Tom Stellard <tom at stellard.net> wrote:
> On Mon, Aug 05, 2013 at 02:09:58PM -0400, Francois Pichet wrote:
> > On my target store/load of f32 or i32 are equivalents.
> > Previously I had duplicate instructions def in .td to map f32 and i32 to
> > the same opcode.
> >
> > I deleted all that and I instead tried a new approach
2012 Jul 16
3
[LLVMdev] RFC: LLVM incubation, or requirements for committing new backends
...unk/lib/Target/AMDGPU/Makefile
> llvm/trunk/lib/Target/AMDGPU/Processors.td
> llvm/trunk/lib/Target/AMDGPU/R600CodeEmitter.cpp
> llvm/trunk/lib/Target/AMDGPU/R600GenRegisterInfo.pl
> llvm/trunk/lib/Target/AMDGPU/R600HwRegInfo.include
> llvm/trunk/lib/Target/AMDGPU/R600ISelLowering.cpp
> llvm/trunk/lib/Target/AMDGPU/R600ISelLowering.h
> llvm/trunk/lib/Target/AMDGPU/R600InstrInfo.cpp
> llvm/trunk/lib/Target/AMDGPU/R600InstrInfo.h
> llvm/trunk/lib/Target/AMDGPU/R600Instructions.td
> llvm/trunk/lib/Target/AMDGPU/R600Intrinsics.td
> llvm/...