search for: r600_pred

...dify the instruction patterns to make this work. For example, I have the class: class R600_1OP <bits<32> inst, string opName, list<dag> pattern, InstrItinClass itin = AnyALU> : InstR600 <inst, (outs R600_Reg32:$dst), (ins R600_Reg32:$src, R600_Pred:$p, i32imm:$flags), !strconcat(opName, " $dst, $src ($p)"), pattern, itin >; And an instruction def: def CEIL : R600_1OP < 0x12, "CEIL", [(set R600_Reg32:$dst, (fceil R600_Reg32:$src))] >; Tablegen fails to compile this with an err...

All, The code generator operand class, MachineOperand, has an 8-bit TargetFlags field that the individual targets can use as they please. X86 and ARM use it to encode linker magic on symbol operands. It has been mentioned a couple of times on this list that it is not safe to use TargetFlags on register operands. This is because many target-independent passes are manipulating register operands

...rns to make this work. For example, I have the class: > > class R600_1OP <bits<32> inst, string opName, list<dag> pattern, > InstrItinClass itin = AnyALU> : > InstR600 <inst, > (outs R600_Reg32:$dst), > (ins R600_Reg32:$src, R600_Pred:$p, i32imm:$flags), > !strconcat(opName, " $dst, $src ($p)"), > pattern, > itin >> ; > > And an instruction def: > > def CEIL : R600_1OP < > 0x12, "CEIL", > [(set R600_Reg32:$dst, (fceil R600_Reg32:$src))] >&g...

...e, I have the > class: > > > > class R600_1OP <bits<32> inst, string opName, list<dag> pattern, > > InstrItinClass itin = AnyALU> : > > InstR600 <inst, > > (outs R600_Reg32:$dst), > > (ins R600_Reg32:$src, R600_Pred:$p, i32imm:$flags), > > !strconcat(opName, " $dst, $src ($p)"), > > pattern, > > itin > >> ; > > > > And an instruction def: > > > > def CEIL : R600_1OP < > > 0x12, "CEIL", > > [(set R...