Displaying 5 results from an estimated 5 matches for "r600_1op".
2012 Aug 21
0
[LLVMdev] No more TargetFlags on MO_Register MachineOperands
...e using extra immediate operands to encode register flags.
>
Hi,
I've been working on replacing the MachineOperand flags in the R600
backend with immediate operands, but I can't figure out how to modify
the instruction patterns to make this work. For example, I have the class:
class R600_1OP <bits<32> inst, string opName, list<dag> pattern,
InstrItinClass itin = AnyALU> :
InstR600 <inst,
(outs R600_Reg32:$dst),
(ins R600_Reg32:$src, R600_Pred:$p, i32imm:$flags),
!strconcat(opName, " $dst, $src ($p)"),...
2012 Aug 20
2
[LLVMdev] No more TargetFlags on MO_Register MachineOperands
All,
The code generator operand class, MachineOperand, has an 8-bit TargetFlags field that the individual targets can use as they please. X86 and ARM use it to encode linker magic on symbol operands.
It has been mentioned a couple of times on this list that it is not safe to use TargetFlags on register operands. This is because many target-independent passes are manipulating register operands
2012 Aug 21
2
[LLVMdev] No more TargetFlags on MO_Register MachineOperands
...rd <thomas.stellard at amd.com> wrote:
> I've been working on replacing the MachineOperand flags in the R600
> backend with immediate operands, but I can't figure out how to modify
> the instruction patterns to make this work. For example, I have the class:
>
> class R600_1OP <bits<32> inst, string opName, list<dag> pattern,
> InstrItinClass itin = AnyALU> :
> InstR600 <inst,
> (outs R600_Reg32:$dst),
> (ins R600_Reg32:$src, R600_Pred:$p, i32imm:$flags),
> !strconcat(opName, " $dst, $src...
2012 Aug 22
2
[LLVMdev] No more TargetFlags on MO_Register MachineOperands
...gt; wrote:
>
> > I've been working on replacing the MachineOperand flags in the R600
> > backend with immediate operands, but I can't figure out how to modify
> > the instruction patterns to make this work. For example, I have the
> class:
> >
> > class R600_1OP <bits<32> inst, string opName, list<dag> pattern,
> > InstrItinClass itin = AnyALU> :
> > InstR600 <inst,
> > (outs R600_Reg32:$dst),
> > (ins R600_Reg32:$src, R600_Pred:$p, i32imm:$flags),
> > !strconcat(...
2012 Oct 15
2
[LLVMdev] Alternate instruction encoding for subtargets
Hello,
I have a compiler in LLVM 2.9 for the KCPM3 processor. I'd like to
create a subtarget for the new cpu version called KCPSM6. Besides a
couple of new instructions which are not important at the moment, the
KCPSM6 cpu has different instruction opcodes. Semantically the
instructions are the same, hence I'd like to keep all the lowering and
pattern matching stuff unmodified
For