search for: r57565

...nly > does 32 bit aligned loads and things have "just worked", but I've got > my sights set higher now (load of bytes, store of 4 x byte vectors, > etc). What version of LLVM are you using? I recently made some tablegen changes to allow nodes to have multiple predicates. See r57565 for an example of a change made possible by being able to have multiple predicates on a node, and it sounds similar to what you describe. > > > (2) The HW I'm targeting does not have byte/short load/store; the > finest granularity is aligned 32 bit load/store (like the original &gt...

I've been running into two issues with load/store handling: (1) is that tablegen doesn't seem to handle the two predicates that get attached to my instructions. The first is the predicate in TargetSelectionDAG.td, identifying a load node as, say, extloadi8. The second is my identification of the load as having a particular address space (need different instructions for different