Displaying 20 results from an estimated 659 matches for "r5".
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rc5
2007 Dec 02
2
Optimised qmf_synth and iir_mem16
...coef_t *den,
@ spx_word16_t *y,
@ int N,
@ int ord,
@ spx_mem_t *mem,
@ char *stack)
.global iir_mem16
iir_mem16:
stmdb sp!, { r4-r11, lr }
ldr r5, [sp, #36] @ r0 = x, r1 = den, r2 = y, r3 = N
ldr r4, [sp, #40] @ r4 = mem, r5 = ord
cmp r5, #10
beq .order_10
cmp r5, #8
beq .order_8
ldmia sp!, { r4-r11, pc } @ Mon-supported order, return
@ TODO: try using direct form 1 f...
2020 Jun 25
2
How to implement load/store for vector predicate register
...pr) for vector predicate registers in backend.
Although there is no direct instruction to move vpr to vr or to move vr to vpr, there is a method to work around this. And we have load/store instructions for vr.
move vpr to vr for v32i16 (from vpr0 to vr1):
1 vclr vr0 // clear vr0
2 ldi r5, 0x00010001 // load immediate (compare bit mask for v32i16) to scalar register r5
3 movr2vr.dup vr2, r5 // duplicate content in r5 into vr2,
4 vadd.t.s16 vr1, vr0, vr2, vpr0 //vector add if element compare bit is set, element type is 16 bit signed integer, now we have moved compare...
2020 Apr 18
2
Debug symbols are missing in elf
...MCTarget layer a lot but not able to find the root-cause.
Any clue is much appreciated.
ex:
hello.c
int main()
{
printf("Hello World\n\r");
printf("Successfully ran Hello World application");
return 0;
}
hello.o objdump:
int main()
{
0: 10a00000 addk r5, r0, r0
4: f8a1002c swi r5, r1, 44
printf("Hello World\n\r");
8: b0000000 imm 0
8: R_MICROBLAZE_64 .rodata.str1.1
c: a0c00000 ori r6, r0, 0
10: f8a10028 swi r5, r1, 40
14: b0000000...
2010 Nov 21
2
boxplot: reverse y-axis order
...24 C 5 1.2
11 02-Jun-99 1.388872027 US C5 NA C 5 1.2
12 09-Aug-04 3.68320322 US C5 9.55 C 5 1.2
12 04-Aug-03 2.739135981 US C5 7.86 C 5 1.2
12 09-Jun-03 1.545336008 US C5 13.3 C 5 1.2
12 09-Aug-00 1.672227979 US C5 13.1 C 5 1.2
12 17-Aug-99 1.449324012 US C5 14.8 C 5 1.2
20 04-Aug-03 2.336800098 US R5 13.3 R 5 1.2
20 09-Jun-03 1.556003928 US R5 13 R 5 1.2
20 01-Jun-01 1.075943947 US R5 18.5 R 5 1.2
20 10-Aug-00 1.355597973 US R5 19.7 R 5 1.2
20 11-Aug-99 0.349300802 US R5 21 R 5 1.2
20 02-Jun-99 0.525272012 US R5 NA R 5 1.2
200 17-Aug-00 4.824984074 US R5 2.53 R 5 1.2
201 29-May-02 NA US R5 7.54...
2020 Apr 18
2
Debug symbols are missing in elf
....c
>> int main()
>> {
>> printf("Hello World\n\r");
>> printf("Successfully ran Hello World application");
>> return 0;
>> }
>>
>> hello.o objdump:
>> int main()
>> {
>> 0: 10a00000 addk r5, r0, r0
>> 4: f8a1002c swi r5, r1, 44
>>
>> printf("Hello World\n\r");
>> 8: b0000000 imm 0
>> 8: R_MICROBLAZE_64 .rodata.str1.1
>> c: a0c00000 ori r6, r0, 0
>> 10:...
2020 Sep 23
2
Incorrect Cortex-R4/R4F/R5 ProcessorModel in ARM.td
In ARM.td, I see that the ProcessorModel for cortex-r4, cortex-r4f, and cortex-r5 (as well as r7 and r8) is based on "CortexA8Model", which seems incorrect. When this was added in 2015, there were also comments associated with this configuration, such as "// FIXME: R5 has currently the same ProcessorModel as A8" (later removed). The processor model for Cort...
2020 Apr 20
2
Debug symbols are missing in elf
...o World\n\r");
>>>> printf("Successfully ran Hello World application");
>>>> return 0;
>>>> }
>>>>
>>>> hello.o objdump:
>>>> int main()
>>>> {
>>>> 0: 10a00000 addk r5, r0, r0
>>>> 4: f8a1002c swi r5, r1, 44
>>>>
>>>> printf("Hello World\n\r");
>>>> 8: b0000000 imm 0
>>>> 8: R_MICROBLAZE_64 .rodata.str1.1
>>>> c:...
2015 May 21
2
[LLVMdev] How can I remove these redundant copy between registers?
Hi,
I've been working on a Blackfin backend (llvm-3.6.0) based on the previous
one that was removed in llvm-3.1.
llc generates codes like this:
29 p1 = r2;
30 r5 = [p1];
31 p1 = r2;
32 r6 = [p1 + 4];
33 r5 = r6 + r5;
34 r6 = [p0 + -4];
35 r5 *= r6;
36 p1 = r2;
37 r6 = [p1 + 8];
38 p1 = r2;
p1 and r2 are in different register classes.
A p* register can be used for load/stroe values from memory while a r*
register can...
2020 Jun 26
2
How to implement load/store for vector predicate register
...pr) for vector predicate registers in backend.
Although there is no direct instruction to move vpr to vr or to move vr to vpr, there is a method to work around this. And we have load/store instructions for vr.
move vpr to vr for v32i16 (from vpr0 to vr1):
1 vclr vr0 // clear vr0
2 ldi r5, 0x00010001 // load immediate (compare bit mask for v32i16) to scalar register r5
3 movr2vr.dup vr2, r5 // duplicate content in r5 into vr2,
4 vadd.t.s16 vr1, vr0, vr2, vpr0 //vector add if element compare bit is set, element type is 16 bit signed integer, now we have moved compare...
2004 Sep 10
1
altivec lpc_restore_signal
...us the Destruct-O-Beam!
-------------- next part --------------
; $Name$ $Revision$ $Date$
.text
.align 2
.globl _FLAC__lpc_restore_signal_asm_ppc_altivec_16
.globl _FLAC__lpc_restore_signal_asm_ppc_altivec_16_order8
_FLAC__lpc_restore_signal_asm_ppc_altivec_16:
; r3: residual[]
; r4: data_len
; r5: qlp_coeff[]
; r6: order
; r7: lp_quantization
; r8: data[]
; see src/libFLAC/lpc.c:FLAC__lpc_restore_signal()
; these is a PowerPC/Altivec assembly version which requires bps<=16 (or actual
; bps<=15 for mid-side coding, since that uses an extra bit)
; these should be fast; the inner loop...
2013 Oct 03
1
[LLVMdev] Help with a Microblaze code generation problem.
...swi r0, r19, 16
addik r3, r0, -2147483648
swi r3, r19, 24
swi r0, r19, 28
lwi r4, r19, 16
xor r3, r4, r3
lwi r4, r19, 20
or r3, r4, r3
addik r4, r0, 0
addik r5, r0, 1
swi r5, r19, 32
beqid r3, ($BB0_2)
swi r4, r19, 36
lwi r3, r19, 36
swi r3, r19, 32
$BB0_2:
lwi r3, r19, 32
add r1, r19, r0
lwi r19, r1, 4
rtsd r15, 8
a...
2005 Jul 20
1
MMX IDCT for theora-exp
...r2","r4"\n" \
+ " movq " J(5)","r7"\n" \
+ " pmulhw " r6","r4"\n" \
+ " movq " C(5)","r1"\n" \
+ " pmulhw " r7","r6"\n" \
+ " movq " r1","r5"\n" \
+ " pmulhw " r2","r1"\n" \
+ " movq " I(1)","r3"\n" \
+ " pmulhw " r7","r5"\n" \
+ " movq " C(1)","r0"\n" \
+ " paddw " r2","r4"\n"...
2017 Nov 05
2
What pattern string corresponds to CopyToReg?
...gt;> entry:
>> ret i16 127
>> }
>>
>> ------- debug output --------
>>
>> Optimized legalized selection DAG: BB#0 'my_func:entry'
>> SelectionDAG has 5 nodes:
>> t0: ch = EntryToken
>> t3: ch,glue = CopyToReg t0, Register:i16 %R5, Constant:i16<127>
>> t4: ch = TMS9900ISD::Ret t3, Register:i16 %R5, t3:1
>>
>> ===== Instruction selection begins: BB#0 'entry'
>> Selecting: t4: ch = TMS9900ISD::Ret t3, Register:i16 %R5, t3:1
>>
>> ISEL: Starting pattern match on root node: t4:...
2016 May 12
2
[LLVMdev] Improving the quality of debug locations / DbgValueHistoryCalculator
> On May 12, 2016, at 11:00 AM, Francois Pichet <pichet2000 at gmail.com> wrote:
>
> Here is a specific case that make the debugging experiences degraded on my target:
> This is a loop simplified CFG:
>
> BB#0:
> %R5<def> = OR_rr %R0, %R49 // this is %R5 only def.
> DBG_VALUE %R5, %noreg, !"argc", <!18>; line no:4
> Successors according to CFG: BB#1
>
> BB#1:
> Live Ins: %R5
> Predecessors according to CFG: BB#0 BB#3
> ...
> Successors acco...
2017 Oct 20
1
[PATCH v1 01/27] x86/crypto: Adapt assembly for PIE support
...6_64-asm_64.S
>> +++ b/arch/x86/crypto/aes-x86_64-asm_64.S
>> @@ -48,8 +48,12 @@
>> #define R10 %r10
>> #define R11 %r11
>>
>> +/* Hold global for PIE suport */
>> +#define RBASE %r12
>> +
>> #define prologue(FUNC,KEY,B128,B192,r1,r2,r5,r6,r7,r8,r9,r10,r11) \
>> ENTRY(FUNC); \
>> + pushq RBASE; \
>> movq r1,r2; \
>> leaq KEY+48(r8),r9; \
>> movq r10,r11; \
>> @@ -74,54 +78,63 @@
&g...
2017 Oct 20
1
[PATCH v1 01/27] x86/crypto: Adapt assembly for PIE support
...6_64-asm_64.S
>> +++ b/arch/x86/crypto/aes-x86_64-asm_64.S
>> @@ -48,8 +48,12 @@
>> #define R10 %r10
>> #define R11 %r11
>>
>> +/* Hold global for PIE suport */
>> +#define RBASE %r12
>> +
>> #define prologue(FUNC,KEY,B128,B192,r1,r2,r5,r6,r7,r8,r9,r10,r11) \
>> ENTRY(FUNC); \
>> + pushq RBASE; \
>> movq r1,r2; \
>> leaq KEY+48(r8),r9; \
>> movq r10,r11; \
>> @@ -74,54 +78,63 @@
&g...
2013 Jan 21
1
[LLVMdev] Mapping registers into memory address
...de for Android's Dalvik VM.
I translated some DEX bytecode to LLVM IR, and now I wnat to translate
these IR into ARM assembly by using llc.
But there are some ABI problems (Register mapping) should be solved.
Dalvik VM stores virtual register in the fixed memory address.
For example,
v0 -> [r5,#0]
v1 -> [r5,#4]
v2 -> [r5,#8]
v3 -> [r5,#12]
....
v100 -> [r5,#400]
So I want to know how can I generate such register allocation?
(e.g load v3 from [r5,#12] and store v2 into [r5,#8])
I have got the approach for reserving r5, but load/store problem not yet
Is there any related info...
2012 Feb 13
0
[PATCH 05/14] arm: implement exception and hypercall entries.
...);
+ DEFINE(OFFSET_VCPU_R1, offsetof(struct vcpu_guest_context, r1));
+ DEFINE(OFFSET_VCPU_R2, offsetof(struct vcpu_guest_context, r2));
+ DEFINE(OFFSET_VCPU_R3, offsetof(struct vcpu_guest_context, r3));
+ DEFINE(OFFSET_VCPU_R4, offsetof(struct vcpu_guest_context, r4));
+ DEFINE(OFFSET_VCPU_R5, offsetof(struct vcpu_guest_context, r5));
+ DEFINE(OFFSET_VCPU_R6, offsetof(struct vcpu_guest_context, r6));
+ DEFINE(OFFSET_VCPU_R7, offsetof(struct vcpu_guest_context, r7));
+ DEFINE(OFFSET_VCPU_R8, offsetof(struct vcpu_guest_context, r8));
+ DEFINE(OFFSET_VCPU_R9, offsetof(struct vcpu...
2016 Nov 17
2
Loop invariant not being optimized
...to read, here's
what I see (LVM 3.9, compiling with: clang -fms-compatibility
-funroll-loops -O3 -c fma.c -o fma.o )
0000000000000000 <f1>:
0: 29580c0000000000 load r3,r0,0x0,64
8: 2958100200000000 load r4,r1,0x0,64 #r4 <- a[0][0]
10: 2958140400000000 load r5,r2,0x0,64
18: c0580c0805018000 fmaf r3,r4,r5,r3,64
20: 79b80c0000000000 store r3,r0,0x0,64
28: 2958100000000008 load r4,r0,0x8,64
30: 2958140200000000 load r5,r1,0x0,64 #r5 <- a[0][0]
38: 2958180400000008 load r6,r2,0x8,64
40: c058100a06020000 fmaf...
2017 Nov 05
2
What pattern string corresponds to CopyToReg?
..."
; Function Attrs: noinline nounwind optnone
define signext i16 @my_func() #0 {
entry:
ret i16 127
}
------- debug output --------
Optimized legalized selection DAG: BB#0 'my_func:entry'
SelectionDAG has 5 nodes:
t0: ch = EntryToken
t3: ch,glue = CopyToReg t0, Register:i16 %R5, Constant:i16<127>
t4: ch = TMS9900ISD::Ret t3, Register:i16 %R5, t3:1
===== Instruction selection begins: BB#0 'entry'
Selecting: t4: ch = TMS9900ISD::Ret t3, Register:i16 %R5, t3:1
ISEL: Starting pattern match on root node: t4: ch = TMS9900ISD::Ret t3,
Register:i16 %R5, t3:1...