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2005 Apr 20
1
[LLVMdev] adding new instructions to support "swizzle" and "writemask"
...supports swizzle and writemask. I have a few solutions: (1) Treat each channel of a register as a individual SSA variable. This could generate inefficient machine code. For example, the instruction: add r0.xz, r1.y, r2.wx is translated to two LLVM instructions: r0_x = add float r1_y, r2_w r0_z = add float r1_y, r2_x Subsequent optimization passes could insert other instructions between these two instruction (for example, in instruction scheduling pass). I don't know how they could be easily merged back into one instruction. It could lead to inefficient machine code (though...