search for: r2_r3

...banks now, and we even use registers to model some encoding constraints. For example, a few ARM instructions like strexd have two register operands that must be an aligned pair of consecutive GPR registers (like r0, r1). This constraint is modeled with the GPRPair register class containing R0_R1, R2_R3, ... pseudo-registers. Sometimes ISAs also assign assembly names to such pseudo-registers, again from ARM: SPR: (s0, s1, ...) 32-bit floating point registers. DPR: (d0, d1, ...) Even-odd pairs of consecutive S-registers. QPR: (q0, q1, ...) Even-odd pairs of consecutive D-registers. But not all c...

...ill>, %R0_R1<imp-def> <<<<<<<<<<<<<<<<<<<<< INLINEASM <es:3: ldaexd $0, ${0:H}, [$2]; strexd $1, $3, ${3:H}, [$2]; cmp $1,#0; bne 3b;> [sideeffect] [mayload] [maystore] [attdialect], $0:[regdef-ec:GPRPair], %R2_R3<earlyclobber,def,dead>, $1:[regdef-ec:GPRPair], %R6_R7<earlyclobber,def,dead>, $2:[reguse:GPR], %R4<kill>, $3:[reguse:GPRPair], %R0_R1<kill>, <!11> CMPri %R12<kill>, 1, pred:14, pred:%noreg, %CPSR<imp-def> // Second comparison with lock_flag; R12 h...

..., and we even use registers to model some encoding constraints. > > For example, a few ARM instructions like strexd have two register operands that must be an aligned pair of consecutive GPR registers (like r0, r1). This constraint is modeled with the GPRPair register class containing R0_R1, R2_R3, ... pseudo-registers. > > Sometimes ISAs also assign assembly names to such pseudo-registers, again from ARM: > > SPR: (s0, s1, ...) 32-bit floating point registers. > DPR: (d0, d1, ...) Even-odd pairs of consecutive S-registers. > QPR: (q0, q1, ...) Even-odd pairs of consecuti...