Displaying 5 results from an estimated 5 matches for "r27r26".
2011 Mar 25
2
[LLVMdev] Possible missed optimization?
...uot;int")
PTRREGS:%vreg5 DLDREGS:%vreg3
RET
>From above, the 3rd COPY instruction is redundant since it does exactly the
same thing as the second COPY instruction, so the stw (store) instr should
take %vreg2 instead of %vreg5. After regalloc we get this code:
Live Ins: %R25R24
%R27R26<def> = COPY %R25R24
%R19R18<def> = LDWRd %R27R26<kill>; mem:LD2[%a](align=1)(tbaa=!"int") //
<---------- why is R27:R26 killed?
%R19R18<def> = ANDIWRdK %R19R18, 255
%R27R26<def> = COPY %R25R24<kill> // <------------------ why is this
e...
2011 Mar 26
0
[LLVMdev] Possible missed optimization?
On Mar 24, 2011, at 5:42 PM, Borja Ferrer wrote:
> The last copy instruction should be removed as pointed out above, but since R27R26 is killed in the load instruction it has to be emitted. About the insane amount of regclasses there, the load/store and the andi instructions take subsets of regs from the main register class, they cant work with all registers, that's why STW and LDW needs R27R26 since it belongs to the ptr reg...
2015 Jan 31
3
[LLVMdev] Encoding instructions with inconsistent formats
...10`
ld Rd, Z `1000 000d dddd 0000`
ld Rd, Z+ `1001 000d dddd 0001`
ld Rd, -Z `1001 000d dddd 0010`
^
|
Note this one inconsistent bit
One way to solve this solution would be to to describe them in InstrInfo.td
as seperate instructions. Note that R27R26 is a pointer register defined in
AVRRegisterInfo.td, and 'X' is an alias for this.
let Uses = [R27R26],
canFoldAsLoad = 1,
isReMaterializable = 1 in
def LDRdX : FSTLDPtrReg<0b0,
(outs GPR8:$reg),
(ins),
&quo...
2011 Mar 26
2
[LLVMdev] Possible missed optimization?
...he three regclasses involved here are
all subsets from each other and aren't disjoint. These are the basic
descriptions of the regclasses involved to show what i mean:
DREGS: R31R30, R29R28 down to R1R0 (16 regs)
DLDREGS: R31R30, R29R28 down to R17R16 (8 regs)
PTRREGS: R31R30, R29R28, R27R26 (3 regs)
All classes intersect each other giving as a result the smaller class:
DREGSxDLDREGS=DLDREGS / DLDREGSxPTRREGS=PTRREGS, etc. That's why i think the
coalescer should work since the regclasses overlap completely.
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2011 Mar 26
0
[LLVMdev] Possible missed optimization?
...involved here are all subsets from each other and aren't disjoint. These are the basic descriptions of the regclasses involved to show what i mean:
>
> DREGS: R31R30, R29R28 down to R1R0 (16 regs)
> DLDREGS: R31R30, R29R28 down to R17R16 (8 regs)
> PTRREGS: R31R30, R29R28, R27R26 (3 regs)
>
> All classes intersect each other giving as a result the smaller class: DREGSxDLDREGS=DLDREGS / DLDREGSxPTRREGS=PTRREGS, etc. That's why i think the coalescer should work since the regclasses overlap completely.
Cross class coalescing also has some heuristics to...