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r256b_1
2017 Jul 07
2
Unhandled reg/opcode register encoding VR2048 Error in backend
...R : I<0x7F, MRMDestMem, (outs), (ins i32mem:$dst,
VR2048:$src),
"vmov_256B_mr\t{$src, $dst|$dst, $src}",
[(store (i32 (bitconvert VR2048:$src)), addr:$dst)],
IIC_MOV_MEM>, EVEX;
here i have already define VR2048 in x86registerinfo.td as;
def R256B_0: X86Reg<"R256B_0", 0>;
def R256B_1: X86Reg<"R256B_1", 1>;
def VR2048 : RegisterClass<"X86", [v64i32],
2048, (add R256B_0, R256B_1)
Now when build llvm source i am getting following error:
Unhandled reg/opcode register encodin...